Method and system for controlling a delay of packet processing using loop paths

• US 9,270,595 B2
• Filed: 10/10/2008
• Issued: 02/23/2016
• Est. Priority Date: 10/10/2008
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Hiscock, James S.
• Primary Examiner(s): Lai, Andrew
• Assistant Examiner(s): ANDREWS, LEON T
• Application Number:
  US12/249,244
• Publication Number:
  US 20100091782A1
• Time in Patent Office: 2,692 Days
• Field of Search: 370/244, 370/247, 370/250, 370/251, 370/252, 370/356, 370/394, 370/912
• US Class Current: 1/1
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/283 in response to processing delays, e.g. caused by jitter or round trip time [RTT]
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

A method and system for introducing controlled delay of packet processing at a network device using one or more delay loop paths (DLPs). For each packet received at the network device, a determination will be made as to whether or not packet processing should be delayed. If delay is chosen, a DLP will be selected according to a desired delay for the packet. The desired delay value is used to determine a time value and inserts the time value in the DLP ahead of the packet. Upon completion of a DLP delay, a packet will be returned for processing, an additional delay, or some other action. One or more DLPs may be enabled with packet queues, and may be used advantageously by devices, for which in-order processing of packets may be desired or required.

Claims

1. A method of introducing controlled delay in the processing of packets in a packet-switched data network, the method comprising:

determining that a packet should be delayed before being processed;

determining a desired delay value for the packet;

adding a time field in front of the packet in a first-in-first-out (FIFO) packet queue, said time field containing the desired delay value for the packet to associate a time value with the packet based on the desired delay value;

sending the packet on a delay loop path (DLP); and

removing, by a processor, the packet from the DLP when the time value associated with the packet indicates that the desired delay value has been reached.

2. The method of claim 1, wherein the removing further comprises;

comparing the time value to a system time and;

removing the packet if the time value is a time less than or equal to the system time.

3. The method of claim 1, wherein sending the packet on the DLP comprises inserting the packet in an ordered list of packets.

4. The method of claim 3, wherein the ordered list of packets is ordered by the time value associated with the packet on the DLP.

5. The method of claim 1, wherein the DLP comprises the FIFO packet queue and wherein sending the packet on the DLP comprises:

adding the packet to the FIFO packet queue; and

wherein adding a time field in front of the packet in the FIFO packet queue to associate a time value with the packet further comprises;

writing the time value to the FIFO packet queue before adding the packet to the FIFO packet queue.

6. The method of claim 1, wherein the DLP comprises multiple FIFO packet queues, and wherein sending the packet on the DLP further comprises:

selecting one of the multiple FIFO packet queues;

adding the packet to the selected FIFO packet queue; and

wherein the adding a time field in front of the packet in the FIFO packet queue to associate a time value with the packet further comprises;

writing the time value to the selected FIFO packet queue before writing the packet to the selected FIFO packet queue.

7. The method of claim 6, wherein the multiple FIFO packet queues are each assigned a delay value, and wherein selecting one of the multiple FIFOs further comprises:

comparing an assigned delay value for each DLP with the desired delay value of the packet; and

selecting the FIFO packet queue of the multiple FIFO packet queues having an assigned delay value that is closest in value to the desired delay.

8. The method of claim 1, wherein the determining that the packet should be delayed further comprises:

determining at least one property of the packet.

9. The method of claim 8, wherein determining at least one property of the packet comprises:

inspecting data in the packet; and

determining a relationship of the packet with one or more previously received packets.

10. The method of claim 9, wherein determining the at least one property of the packet further comprises:

determining that the packet is one of a plurality of packets in an ordered sequence and that the packet is out of order with respect to at least one other packet in the ordered sequence.

11. The method of claim 9, wherein determining the at least one property of the packet further comprises:

determining that the packet is one of a plurality of packets in a sequence and that the packet should be delayed to pace the traffic of the packet sequence.

12. A packet processing apparatus with packet delay circuitry comprising:

a memory storing machine readable instructions to;

determine that a packet should be delayed before the packet is processed or forwarded;

determine a desired delay value for the packet;

add a time field in front of the packet in a first-in-first out (FIFO) packet queue, said time field containing the desired delay value for the packet to associate a time value with the packet;

send the packet on a delay loop path (DLP); and

remove the packet from the DLP when the time value associated with the packet indicates that the desired delay value has been reached; and

a processor to implement the machine readable instructions.

13. The packet processing apparatus of claim 12, wherein the packet delay circuitry comprises a field-programmable gate array (FPGA).

14. The packet processing apparatus of claim 12, wherein the packet delay circuitry comprises an application-specific integrated circuit (ASIC).

15. The packet processing apparatus of claim 12, wherein the packet delay circuitry is implemented as a combination of hardware and software.

16. The packet processing apparatus of claim 12, wherein the DLP is implemented as an ordered list of packets.

17. The packet processing apparatus of claim 12, wherein the DLP comprises the FIFO packet queue.

18. The packet processing apparatus of claim 12, wherein the packet processing apparatus is an intrusion prevention system (IPS).

19. The packet processing apparatus of claim 12, wherein the packet processing apparatus connects a public network to a local area network (LAN).

20. The packet processing apparatus of claim 12, wherein the packet processing apparatus is a virtual private network (VPN) device.

21. The packet processing apparatus of claim 12, wherein the packet processing apparatus is an Ethernet switch.

22. The packet processing apparatus of claim 12, wherein the packet processing apparatus is a firewall.

23. The packet processing apparatus of claim 12, wherein the packet processing apparatus is an intelligent network adapter.