Exposure time selection using stacked-chip image sensors

• US 9,270,906 B2
• Filed: 05/02/2013
• Issued: 02/23/2016
• Est. Priority Date: 05/02/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Peng, Honghong, Keelan, Brian
• Primary Examiner(s): DAGNEW, MEKONNEN D
• Application Number:
  US13/875,549
• Publication Number:
  US 20130293752A1
• Time in Patent Office: 1,027 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H04N 23/684 performed by controlling the image sensor readout, e.g. by controlling the integration time
• CPC Class Codes: H04N 23/6845 by combination of a plurality of images sequentially taken
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels and processing circuitry. The image pixel array may be coupled to the processing circuitry through an array of vertical metal interconnects. The image pixel array may be partitioned into image pixel sub-arrays configured to capture image data using one or more integration times. The processing circuitry may determine motion information for the image data captured by each pixel sub-array and may determine integration times for each pixel sub-array. The pixel sub-arrays may capture additional image data using the determined integration times. The additional image data may be combined to generate final image frames having short integration pixel values and long integration pixel values. The processing circuitry may output the final image frames to off-chip image processing circuitry.

Claims

1. A method for operating a stacked-chip image sensor, wherein the stacked-chip image sensor comprises a planar array of image sensor pixels, an array of vertical conductive vias, and processing circuitry coupled to the planar array of image sensor pixels through the array of vertical conductive vias, the method comprising:

with the image sensor pixels, capturing a first set of image data;

providing the captured first set of image data to the processing circuitry using the array of vertical conductive vias;

with the processing circuitry, storing the first set of image data;

with the image sensor pixels, capturing a second set of image data;

with the processing circuitry, determining a motion score for the second set of image data by comparing the second set of image data to the stored first set of image data; and

with the processing circuitry, generating an output image using the determined motion score, wherein the output image has a first region with a first effective integration time and a second region with a second effective integration time.

2. The method defined in claim 1 wherein capturing the first set of image data comprises capturing the first set of image data during a capture integration time.

3. The method defined in claim 2 wherein at least one of the first and second effective integration times is equal to the capture integration time.

4. The method defined in claim 2 wherein at least one of the first and second effective integration times is at least twice the capture integration time.

5. The method defined in claim 2 wherein capturing the second set of image data comprises capturing the second set of image data during the capture integration time, the method further comprising:

comparing the determined motion score to a threshold; and

in response to determining that the motion score is less than the threshold, combining the second set of image data with the stored first set of image data.

6. The method defined in claim 2 wherein capturing the second set of image data comprises capturing the second set of image data during the capture integration time, the method further comprising:

comparing the determined motion score to a threshold; and

in response to determining that the motion score is greater than the threshold, using the stored first set of image data as a portion of the output image.

7. The method defined in claim 2 wherein the planar array of image sensor pixels comprises a first sub-array of image pixels and a second sub-array of image pixels, wherein the first sub-array is associated with the first effective integration time and the second sub-array of image pixels is associated with the second effective integration time, and wherein the first effective integration time and the second effective integration time are integer multiples of the capture integration time.

8. A stacked-chip imaging system, comprising:

a planar array of image sensor pixels, wherein the image sensor pixels captures a first set of image data and a second set of image data;

an array of vertical conductive vias;

processing circuitry coupled to the planar array of image sensor pixels through the array of vertical conductive vias, wherein the planar array of image sensor pixels is configured to provide the captured first and second sets of image data to the processing circuitry over the array of vertical conductive vias, and wherein the processing circuitry is configured to;

store the first set of image data;

determine a motion score for the second set of image data by comparing the second set of image data to the stored first set of image data; and

generate an output image using the determined motion score, wherein the output image has a first region with a first effective integration time and a second region with a second effective integration time.

9. The system defined in claim 8 wherein the first set of image data is captured during a capture integration time.

10. The system defined in claim 9 wherein at least one of the first and second effective integration times is equal to the capture integration time.

11. The system defined in claim 9 wherein at least one of the first and second effective integration times is at least twice the capture integration time.

12. The system defined in claim 9 wherein the second set of image data is captured during the capture integration time and wherein the processing circuitry is further configured to compare the determined motion score to a threshold and combine the second set of image data with the stored first set of image data if the determined motion score is less than the threshold.

13. The system defined in claim 9 wherein the second set of image data is captured during the capture integration time and wherein the processing circuitry is further configured to compare the determined motion score to a threshold and configured to use the stored first set of image data as a portion of the output image if the determined motion score is greater than the threshold.

14. The system defined in claim 9 wherein the planar array of image sensor pixels comprises a first sub-array of image pixels and a second sub-array of image pixels, wherein the first sub-array captures the first image data using the first effective integration time and the second sub-array of image pixels captures the second image data using the second effective integration time, and wherein the first effective integration time and the second effective integration time are integer multiples of the capture integration time.