Bonding method using porosified surfaces for making stacked structures

• US 9,272,899 B2
• Filed: 01/07/2015
• Issued: 03/01/2016
• Est. Priority Date: 07/27/2012
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Singapore Pte. Ltd. (Vanguard International Semiconductor Corporation)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Kotlanka, Rama Krishna, Kumar, Rakesh, Chirayarikathuveedu Sankarapillai, Premachandran, Lin, Huamao, Yelehanka, Pradeep
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Peterson, Erik T
• Application Number:
  US14/591,896
• Publication Number:
  US 20150115453A1
• Time in Patent Office: 419 Days
• Field of Search: 438/960, 257/621, 257/686, 257/777, 257/698
• US Class Current: 1/1
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2201/0115 Porous silicon
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Claims

1. A device comprising:

a first device having a first semiconductor substrate having first and second major surfaces, wherein the first semiconductor substrate comprises

a first bonding region with a first bonding surface, wherein the first bonding surface comprises a porosified region which is part of first substrate material of the first semiconductor substrate and extends from the first major surface of the first semiconductor substrate to a depth shallower than the second major surface of the first semiconductor substrate; and

a second device which comprises a second semiconductor substrate having first and second major surfaces, wherein the second semiconductor substrate comprises

a second bonding region with a second bonding surface, wherein the second bonding surface includes a conductive contact comprising a through silicon via (TSV) contact, wherein

the second bonding surface is aligned to be above and facing the porosified region of the first bonding surface, and

the second bonding surface of the conductive contact is bonded to the first bonding surface with the porosified region.

2. The device of claim 1 wherein the porosified region comprises silicon, germanium or silicon germanium.

3. The device of claim 1 comprising a first metal layer disposed over and in direct contact with the porosified region of the first bonding surface.

4. The device of claim 3 wherein the second bonding surface of the conductive contact is directly bonded to and in direct contact with the first metal layer.

5. The device of claim 3 wherein the first metal layer comprises Titanium (Ti), Copper (Cu) or Aluminum (Al).

6. The device of claim 3 wherein the first metal layer comprises sintered metal or metal nanowires or a combination thereof.

7. The device of claim 3 comprising a second metal layer disposed over and in direct contact with the second bonding surface of the conductive contact.

8. The device of claim 7 wherein the second metal layer is directly bonded to and in direct contact with the first metal layer.

9. The device of claim 7 wherein the first and second metal layers comprise Titanium (Ti), Copper (Cu) or Aluminum (Al).

10. The device of claim 7 wherein the second metal layer comprises sintered metal or metal nanowires or a combination thereof.

11. The device of claim 1 wherein the TSV contact extends from the second major surface to the first major surface of the second semiconductor substrate and has an extended portion which is beyond and above the first major surface of the second semiconductor substrate, wherein the second bonding surface corresponds to an exposed top surface of the extended portion of the TSV contact.

12. The device of claim 11 comprising an interconnect dielectric layer which surrounds side surfaces of the extended portion of the TSV contact without covering the top surface of the extended portion and first major surface of the second semiconductor substrate.

13. The device of claim 1 comprising a second metal layer disposed over top surface of the TSV contact, wherein the second metal layer is directly bonded to and in direct contact with the porosified region of the first bonding surface and forms a eutectic bond between the first and second bonding surfaces.

14. The device of claim 13 wherein the second metal layer comprises Titanium (Ti), Copper (Cu) or Aluminum (Al).

15. The device of claim 13 wherein the second metal layer comprises sintered metal or metal nanowires or a combination thereof.

16. The device of claim 1 wherein the second bonding surface corresponds to an exposed top surface of the TSV contact and the second bonding surface is directly bonded to the first bonding surface with the porosified region and forms a eutectic bond between the first and second bonding surfaces.

17. The device of claim 1 wherein the first substrate comprises a MEMS device and the second substrate comprises a CMOS device.

18. The device of claim 1 wherein the first device comprises a blocking layer disposed over the first major surface of the first semiconductor substrate, the blocking layer defines the first bonding region which corresponds to an area exposed by the blocking layer and the blocking layer prevents porosification of the first substrate material underlying the blocking layer.