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Memory wear control

  • US 9,274,712 B2
  • Filed: 02/25/2014
  • Issued: 03/01/2016
  • Est. Priority Date: 06/23/2009
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a performance governor circuit configured to connect to a memory and configured to control a degree of wear of the memory as a function of at least one selected point in time by;

    computing a wear value of a new command;

    determining whether the computed wear value will cause a current memory wear to exceed a predetermined wear level; and

    if the computed wear value will not cause the current memory wear to exceed the predetermined wear level within a smallest possible command completion time of the new command, then executing the new command.

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