Memory wear control

• US 9,274,712 B2
• Filed: 02/25/2014
• Issued: 03/01/2016
• Est. Priority Date: 06/23/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Feldman, Timothy Richard, Haines, Jonathan Williams, Cook, Brett Alan
• Primary Examiner(s): LI, ZHUO H
• Application Number:
  US14/189,697
• Publication Number:
  US 20140181380A1
• Time in Patent Office: 735 Days
• Field of Search: 711/100, 711102-103, 711/114, 711/154, 711/170, 710/8, 365/189.011, 365/189.14, 365/189.17
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time.

Claims

1. A system comprising:

a performance governor circuit configured to connect to a memory and configured to control a degree of wear of the memory as a function of at least one selected point in time by;

computing a wear value of a new command;

determining whether the computed wear value will cause a current memory wear to exceed a predetermined wear level; and

if the computed wear value will not cause the current memory wear to exceed the predetermined wear level within a smallest possible command completion time of the new command, then executing the new command.

2. The system of claim 1 and wherein the at least one selected point in time comprises a specified lifetime of the memory.

3. The system of claim 2 and wherein the performance governor circuit is configured to obtain the predetermined wear level from a wear versus time profile.

4. The system of claim 3 and wherein the wear versus time profile is a predetermined constant cumulative wear rate.

5. The system of claim 3 and wherein the performance governor circuit is configured to maintain a wear rate the memory at or below the wear versus time profile at all times during the specified lifetime of the memory.

6. The system of claim 3 and wherein the performance governor circuit is configured to maintain a wear rate of the memory at or below the wear versus time profile for at least a portion of the specified lifetime of the memory.

7. The system of claim 3 and wherein the wear versus time profile is calculated after one of a predetermined time from first use of the memory, a predetermined amount of wear of the memory or a predetermined amount of access of the memory.

8. The system of claim 3 and wherein the performance governor circuit is configured to utilize alternative storage methods to prevent a wear of the memory from exceeding the wear versus time profile.

9. The method of claim 4 and wherein the predetermined constant cumulative wear rate is a maximum cumulative wear rate to minimally ensure that the memory meets its specified lifetime.

10. The system of claim 1 and wherein, if the performance governor circuit determines that the wear value will cause the current memory wear to exceed the predetermined wear level within the smallest possible command completion time, then the performance governor circuit effects the execution of the command to have a longer command completion time that allows a resultant current memory wear level not to exceed the predetermined wear level.

11. The system of claim 1 and wherein, if the performance governor circuit determines that the wear value will cause the current memory wear to exceed the predetermined wear level within the smallest possible command completion time, then the performance governor circuit causes the command not to be executed completely and to end with a non-completed status indication.

12. The system of claim 11 and wherein the performance governor circuit is further configured to complete an incomplete portion of the command that was not executed completely, the completion of the incomplete portion of the command is carried out upon receipt of a resubmitted command.

13. A system comprising:

a performance governor circuit configured to connect to a memory and configured to control a degree of wear of the memory as a function of at least one selected point in time by;

determining a wear effect of executing a new command to access the memory on a current memory wear, and

controlling execution of the new command based on the determined wear effect and based on whether the execution of the new command within a smallest possible command completion time of the new command will cause the current memory wear to exceed a predetermined wear level.

14. The system of claim 13 and wherein the performance governor circuit is configured to determine the wear effect of executing the new command to access the memory on the current memory wear by examining a computed wear value for the new command.

15. The system of claim 14 and wherein the performance governor circuit is further configured to obtain the predetermined wear level from a wear versus time profile.

16. The system of claim 15 and wherein the wear versus time profile is a predetermined constant cumulative wear rate.

17. The system of claim 13 and wherein the at least one selected point in time comprises a specified lifetime of the memory.

18. A method comprising:

receiving commands to access a memory;

computing wear values for the received commands; and

controlling execution of the received commands based on the computed wear values and based on whether the execution of each of the received commands within a smallest command completion time of the respective received command will maintain a wear of the memory at or below a wear versus time profile.

19. The method of claim 18 and wherein the wear versus time profile is a predetermined constant cumulative wear rate.

20. The method of claim 19 and wherein the predetermined constant cumulative wear rate is a maximum cumulative wear rate to minimally ensure that the memory meets its specified lifetime.