Methods and apparatus for detecting and correcting errors in high-speed serial communications systems

• US 9,274,880 B1
• Filed: 08/09/2013
• Issued: 03/01/2016
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Mendel, David W., Baeckler, Gregg William
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US13/963,791
• Time in Patent Office: 935 Days
• US Class Current: 1/1
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 2001/0094 Bus

Abstract

An error detection and correction circuit is provided that reduces the number of errors in a data signal sent over a high-speed serial link with little area overhead and without deteriorating the latency of the data transmission. An error detection and correction circuit on the transmit side may compute parity bits for each data packet of N bit-wise interleaved data packets and insert these parity bits into a serial data stream. A transmitter may send the serial data stream with the data packets and the parity bits over a high-speed serial link to a receiver. An error detection and correction circuit on the receive side may locate and correct single-bit errors and detect double-bit errors in each packet of the data signal. Thus, the error correction circuit may correct up to N errors in the N bit-wise interleaved data packets.

Claims

1. Circuitry for reducing errors in a data signal received over a high-speed serial link, wherein the data signal includes multiple groups of bits, and wherein each group of bits includes data bits and parity bits, the circuitry comprising:

an interface circuit that receives the data signal over the high-speed serial link;

an error generating circuit that receives at least a first group of bits of the multiple groups of bits and that generates an error signal based at least in part on a value of at least one additional bit in the first group of bits that is selected between an odd parity bit and an even parity bit; and

an error correction circuit that receives the data signal from the interface circuit and that uses the parity bits to locate and correct only single-bit errors in the data bits of each group of bits in the data signal.

2. The circuitry of claim 1 further comprising:

a transmitter that is coupled to the high-speed serial link and that sends the data signal over the high-speed serial link to the interface circuit.

3. The circuitry of claim 1, wherein the error correction circuit further detects double-bit errors in each group of bits in the data signal.

4. The circuitry of claim 1, wherein the data signal that is received by the interface circuit includes multiple groups of bits that are bit-wise interleaved.

5. The circuitry of claim 1, wherein the error correction circuit further comprises:

a parity generator circuit that receives a given group of bits in the data signal, wherein the parity generator circuit computes additional parity bits based on the data bits in the given group of bits; and

a parity check circuit that receives the parity bits in the given group of bits and the additional parity bits computed from the parity generator circuit, wherein the parity check circuit compares the parity bits in the given group of bits with the additional parity bits and outputs a bit position for a detected single-bit error based on the comparison.

6. The circuitry of claim 5, wherein the error correction circuit further comprises:

correction circuitry that receives the bit position of the single-bit error from the parity check circuit and inverts data at the bit position.

7. Circuitry for encoding a data signal for transmission over a high-speed serial link, wherein the data signal is arranged in groups of bits, the circuitry comprising:

an encoding circuit that generates parity bits and inserts the parity bits into the data signal to enable single-bit error correction in each group of bits upon receipt of the data signal, wherein the encoding circuit includes first and second logic gates that receive respective first and second groups of bits of the data signal that differ in at least one bit, wherein the encoding circuit includes a selector circuit for selecting a value for at least a given bit of the data signal to distinguish between an even parity bit value and an odd parity bit value for each group of bits; and

a transmitter circuit that receives the data signal from the encoding circuit and transmits the data signal over the high-speed serial link.

8. The circuitry of claim 7 further comprising:

a receiver coupled to the high-speed serial link that receives the data signal transmitted over the high-speed serial link.

9. The circuitry of claim 7, wherein the encoding circuit further generates and adds an additional parity bit to each group of bits of the data signal to enable double-bit error detection in each group of bits.

10. The circuitry of claim 7, wherein the encoding circuit further comprises:

an interleaver circuit that receives the groups of bits with parity bits and that bit-wise interleaves a given number of subsequently received groups of bits with parity bits.

11. The circuitry of claim 7,

wherein the even parity bit is high only when a number of set bits in a respective group of bits is odd, and wherein the odd parity bit is low only when the number of set bits in a respective group of bits is odd.

12. The circuitry of claim 11, wherein the selector circuit further comprises:

a multiplexer that receives a control signal, the even parity bit, and the odd parity bit, wherein the multiplexer selects between a first signal value for the value of the given bit to indicate even parity and a second signal value for the value of the given bit to indicate odd parity based on the control signal.

13. The circuitry of claim 7, wherein the encoding circuit further generates additional groups of bits and inserts the generated additional groups of bits into the data signal, and wherein the additional groups of bits convey a command for a receiver of the data signal.

14. The circuitry of claim 13, wherein the command for the receiver of the data signal includes a comma symbol used for synchronization of data signals.

15. The circuitry of claim 13, wherein the encoding circuit further inserts an additional bit into each group of bits and each additional group of bits, and wherein the additional bit has a different value for the additional groups of bits and for the groups of bits.

16. A method for transmitting a serial data signal that comprises bits each having a value selected from a logic low value and a logic high value, the method comprising:

identifying a start of a plurality of packets in the data signal, wherein the packets are bit-wise interleaved;

computing a set of parity bits for each of the plurality of bit-wise interleaved packets;

computing an additional parity bit for a first packet of the plurality of packets by selecting between an odd parity bit and an even parity bit based on an amount of logic low bits in a subset of the data signal;

inserting the sets of parity bits into the data signal; and

transmitting the data signal over a serial communications link.

17. The method of claim 16 further comprising:

with a receiver circuit, receiving the data signal transmitted over the serial communications link;

identifying the start of the plurality of packets, wherein the packets are bit-wise interleaved; and

computing an additional set of parity bits for the plurality of bit-wise interleaved packets.

18. The method of claim 17 further comprising:

for the plurality of bit-wise interleaved packets, comparing the additional set of parity bits with the set of parity bits in the data signal to locate a single-bit error; and

in response to locating the single-bit error, correcting the single-bit error by inverting data at the single-bit error location.

19. A method for receiving a serial data signal comprising:

identifying a start of a plurality of packets in the received data signal, wherein the packets are bit-wise interleaved;

identifying a first set of parity bits for each of the plurality of bit-wise interleaved packets in the received data signal;

identifying an additional parity bit that indicates a parity selected from an odd parity and even parity;

computing a second set of parity bits for each of the plurality of bit-wise interleaved packets; and

for the plurality of bit-wise interleaved packets, comparing the additional set of parity bits with the set of parity bits in the data signal to locate a single-bit error.

20. The method of claim 19 further comprising:

in response to locating the single-bit error, correcting the single-bit error by inverting data at the single-bit error location.