Methods and apparatus for detecting and correcting errors in high-speed serial communications systems
First Claim
1. Circuitry for reducing errors in a data signal received over a high-speed serial link, wherein the data signal includes multiple groups of bits, and wherein each group of bits includes data bits and parity bits, the circuitry comprising:
- an interface circuit that receives the data signal over the high-speed serial link;
an error generating circuit that receives at least a first group of bits of the multiple groups of bits and that generates an error signal based at least in part on a value of at least one additional bit in the first group of bits that is selected between an odd parity bit and an even parity bit; and
an error correction circuit that receives the data signal from the interface circuit and that uses the parity bits to locate and correct only single-bit errors in the data bits of each group of bits in the data signal.
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Accused Products
Abstract
An error detection and correction circuit is provided that reduces the number of errors in a data signal sent over a high-speed serial link with little area overhead and without deteriorating the latency of the data transmission. An error detection and correction circuit on the transmit side may compute parity bits for each data packet of N bit-wise interleaved data packets and insert these parity bits into a serial data stream. A transmitter may send the serial data stream with the data packets and the parity bits over a high-speed serial link to a receiver. An error detection and correction circuit on the receive side may locate and correct single-bit errors and detect double-bit errors in each packet of the data signal. Thus, the error correction circuit may correct up to N errors in the N bit-wise interleaved data packets.
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Citations
20 Claims
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1. Circuitry for reducing errors in a data signal received over a high-speed serial link, wherein the data signal includes multiple groups of bits, and wherein each group of bits includes data bits and parity bits, the circuitry comprising:
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an interface circuit that receives the data signal over the high-speed serial link; an error generating circuit that receives at least a first group of bits of the multiple groups of bits and that generates an error signal based at least in part on a value of at least one additional bit in the first group of bits that is selected between an odd parity bit and an even parity bit; and an error correction circuit that receives the data signal from the interface circuit and that uses the parity bits to locate and correct only single-bit errors in the data bits of each group of bits in the data signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. Circuitry for encoding a data signal for transmission over a high-speed serial link, wherein the data signal is arranged in groups of bits, the circuitry comprising:
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an encoding circuit that generates parity bits and inserts the parity bits into the data signal to enable single-bit error correction in each group of bits upon receipt of the data signal, wherein the encoding circuit includes first and second logic gates that receive respective first and second groups of bits of the data signal that differ in at least one bit, wherein the encoding circuit includes a selector circuit for selecting a value for at least a given bit of the data signal to distinguish between an even parity bit value and an odd parity bit value for each group of bits; and a transmitter circuit that receives the data signal from the encoding circuit and transmits the data signal over the high-speed serial link. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for transmitting a serial data signal that comprises bits each having a value selected from a logic low value and a logic high value, the method comprising:
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identifying a start of a plurality of packets in the data signal, wherein the packets are bit-wise interleaved; computing a set of parity bits for each of the plurality of bit-wise interleaved packets; computing an additional parity bit for a first packet of the plurality of packets by selecting between an odd parity bit and an even parity bit based on an amount of logic low bits in a subset of the data signal; inserting the sets of parity bits into the data signal; and transmitting the data signal over a serial communications link. - View Dependent Claims (17, 18)
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19. A method for receiving a serial data signal comprising:
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identifying a start of a plurality of packets in the received data signal, wherein the packets are bit-wise interleaved; identifying a first set of parity bits for each of the plurality of bit-wise interleaved packets in the received data signal; identifying an additional parity bit that indicates a parity selected from an odd parity and even parity; computing a second set of parity bits for each of the plurality of bit-wise interleaved packets; and for the plurality of bit-wise interleaved packets, comparing the additional set of parity bits with the set of parity bits in the data signal to locate a single-bit error. - View Dependent Claims (20)
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Specification