Method and apparatus for multiple-bit DRAM error recovery

• US 9,274,888 B2
• Filed: 11/15/2013
• Issued: 03/01/2016
• Est. Priority Date: 11/15/2013
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chun, Dexter Tamio, Kim, Jung Pill, Shin, Hyunsuk, Suh, Jungwon
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US14/081,645
• Publication Number:
  US 20150143198A1
• Time in Patent Office: 837 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Claims

1. A system comprising:

a system memory comprising an error detection circuit, the system memory comprising volatile memory;

a memory controller coupled to the system memory;

a processor;

a re-mapper coupled to the processor and to the memory controller, the re-mapper to store mappings of physical page addresses;

a non-volatile memory; and

a memory comprising stored instructions, wherein in response to the error detection circuit detecting a multiple-bit error in a page residing in the system memory, the page having a first physical page address, the stored instructions when executed by the processor cause the system to perform a procedure comprising;

looking up in a page table if a golden page associated with the first physical page address resides in the non-volatile memory;

copying the golden page to a redundant page in the system memory provided the golden page resides in the non-volatile memory, the redundant page having a second physical page address; and

configuring the re-mapper to map the first physical page address to the second physical page address when the processor performs a memory operation indicating the first physical page address, wherein the re-mapper provides the second physical page address to the memory controller.

2. The system of claim 1, the procedure further comprising:

updating a re-map table to store the mapping of the first physical page address to the second physical page address.

3. The system of claim 2, wherein the re-map table is stored in the non-volatile memory.

4. The system of claim 1, the stored instructions comprising further instructions, wherein in response to the error detection circuit detecting and correcting a single-bit error in a second page to provide a corrected page, the second page residing in the system memory and not backed up in the non-volatile memory, the second page having a third physical page address, the further instructions when executed by the processor cause the system to perform a procedure comprising:

storing the corrected page in a second redundant page in the system memory, the second redundant page having a fourth physical page address; and

configuring the re-mapper to map the third physical page address to the fourth physical page address when the processor performs a memory operation indicating the third physical page address, wherein the re-mapper provides the fourth physical page address to the memory controller.

5. The system of claim 4, the procedure further comprising:

updating a re-map table in the non-volatile memory to store the mapping of the first physical page address to the second physical page address; and

updating the re-map table to store the mapping of the third physical page address to the fourth physical page address.

6. The system of claim 1, the system comprising a first die and a second die, the first die comprising the processor, and the second die comprising the system memory and the error detection circuit.

7. The system of claim 1, wherein the system comprises a device selected from a group consisting of a cellular phone, a base station, and a computer system.

8. A non-transitory computer-readable memory comprising stored instructions that, when executed by a processor in response to an error detection circuit detecting a multiple-bit error in a page residing in a volatile memory, cause a system to perform a method comprising:

looking up in a page table stored in the volatile memory if a golden page associated with a physical page address of the page resides in a non-volatile memory;

copying the golden page to a redundant page in the volatile memory provided the golden page resides in the non-volatile memory; and

configuring a re-mapper to map the physical page address of the page to a physical page address of the redundant page when the processor performs a memory operation indicating the physical page address of the page, wherein the re-mapper provides the physical page address of the redundant page to a memory controller of the volatile memory.

9. The non-transitory computer-readable memory of claim 8, the method further comprising:

updating a re-map table in the non-volatile memory to store the mapping of the physical page address of the page to the physical page address of the redundant page.

10. The non-transitory computer-readable memory of claim 9, the method further comprising:

detecting and correcting a single-bit error in a second page residing in the volatile memory for which no corresponding golden page resides in the non-volatile memory;

storing a corrected version of the second page in a second redundant page in the volatile memory; and

configuring the re-mapper to map a physical page address of the second page to a physical page address of the second redundant page when the processor performs a memory operation indicating the physical page address of the second page, wherein the re-mapper provides the physical page address of the second redundant page to the memory controller of the volatile memory.

11. The non-transitory computer-readable memory of claim 10, the method further comprising:

updating the re-map table to store the mapping of the physical page address of the second page to the physical page address of the second redundant page.

12. A method comprising:

detecting by an error detection circuit a multiple-bit error in a page residing in a volatile memory;

looking up in a page table stored in the volatile memory if a golden page associated with a physical page address of the page resides in a non-volatile memory;

copying the golden page to a redundant page in the volatile memory provided the golden page resides in the non-volatile memory; and

configuring a re-mapper to map the physical page address of the page to a physical page address of the redundant page when a memory operation on the volatile memory indicates the physical page address of the page, wherein the re-mapper provides the physical page address of the redundant page to a memory controller of the volatile memory.

13. The method of claim 12, further comprising:

updating a re-map table in the non-volatile memory to store the mapping of the physical page address of the page to the physical page address of the redundant page.

14. The method of claim 13, further comprising:

detecting and correcting by the error detection circuit a single-bit error in a second page residing in the volatile memory for which no corresponding golden page resides in the non-volatile memory;

storing a corrected version of the second page in a second redundant page in the volatile memory; and

configuring the re-mapper to map a physical page address of the second page to a physical page address of the second redundant page when a processor performs a memory operation indicating the physical page address of the second page, wherein the re-mapper provides the physical page address of the second redundant page to the memory controller of the volatile memory.

15. The method of claim 14, further comprising:

updating the re-map table to store the mapping of the physical page address of the second page to the physical page address of the second redundant page.

16. The method of claim 15, further comprising:

loading the re-map table from the non-volatile memory into a local memory of the processor upon a system boot up; and

configuring by the processor the re-mapper based on the re-map table loaded into the local memory.

17. An apparatus comprising:

means for detecting a multiple-bit error in a page residing in a volatile memory;

means for looking up in a page table to determine if a golden page associated with a physical page address of the page resides in a non-volatile memory;

means for copying the golden page to a redundant page in the volatile memory provided the golden page resides in the non-volatile memory; and

means for mapping the physical page address of the page to a physical page address of the redundant page when a memory operation on the volatile memory indicates the physical page address of the page, wherein the means for mapping provides the physical page address of the redundant page to a memory controller of the volatile memory.

18. The apparatus of claim 17, further comprising:

means for updating a re-map table in the non-volatile memory to store the mapping of the physical page address of the page to the physical page address of the redundant page.

19. The apparatus of claim 18, further comprising:

means for detecting and correcting a single-bit error in a second page residing in the volatile memory for which no corresponding golden page resides in the non-volatile memory; and

means for storing a corrected version of the second page in a second redundant page in the volatile memory;

the means for mapping comprising a mapping of a physical page address of the second page to a physical page address of the second redundant page when a memory operation indicates the physical page address of the second page, wherein the means for mapping provides the physical page address of the second redundant page to the memory controller of the volatile memory.

20. The apparatus of claim 19, further comprising:

means for configuring upon a system boot up the means for mapping based on the re-map table.