Decoding method, memory storage device, and memory controlling circuit unit

• US 9,274,891 B2
• Filed: 02/26/2014
• Issued: 03/01/2016
• Est. Priority Date: 12/31/2013
• Status: Active Grant

• Current Assignee: Fujitsu Limited, Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Lin, Wei, Yen, Shao-Wei, Lin, Yu-Hsiang, Lai, Kuo-Hsin
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/190,103
• Publication Number:
  US 20150186212A1
• Time in Patent Office: 734 Days
• Field of Search: 714/763
• US Class Current: 1/1
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1108 Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/3707 Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code

Abstract

A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.

Claims

1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the decoding method comprises:

reading at least one of the memory cells according to a first read voltage to obtain at least one first verification bit;

executing a hard bit mode decoding procedure according to the at least one first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure;

if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the at least one of the memory cells;

deciding a voltage number according to the storage information;

reading the at least one of the memory cells according to a plurality of second read voltages matching the voltage number to obtain a plurality of second verification bits; and

executing a first soft bit mode decoding procedure according to the second verification bits.

2. The decoding method of claim 1, further comprising:

determining whether a second valid codeword is generated by the first soft bit mode decoding procedure;

if the second valid codeword is not generated by the first soft bit mode decoding procedure, increasing the voltage number;

reading the at least one of the memory cells according to a plurality of third read voltages matching the increased voltage number to obtain a plurality of third verification bits; and

executing a second soft bit mode decoding procedure according to the third verification bits.

3. The decoding method of claim 1, wherein data is stored in the at least one of the memory cells, and the step of deciding the voltage number according to the storage information comprises:

estimating an amount of error bits in the data according to the storage information, wherein the voltage number positively correlates the amount of the error bits in the data.

4. The decoding method of claim 1, wherein the storage information comprises a number of erased times of the at least one of the memory cells.

5. The decoding method of claim 1, wherein data is stored in the at least one of the memory cells, and the storage information comprises an elapsed time after storing the data in the at least one of the memory cells.

6. The decoding method of claim 1, wherein data is stored in the at least one of the memory cells, and the storage information comprises a number of read times of the data stored in the at least one of the memory cells.

7. A memory storage device, comprising:

a connection interface unit configured to couple to a host system;

a rewritable non-volatile memory module comprising a plurality of memory cells; and

a memory controlling circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, and configured to read at least one of the memory cells according to a first read voltage to obtain at least one first verification bit, execute a hard bit mode decoding procedure according to the at least one first verification bit, and determine whether a first valid codeword is generated by the hard bit mode decoding procedure,

wherein if the first valid codeword is not generated by the hard bit mode decoding procedure, the memory controlling circuit unit is configured to obtain storage information of the at least one of the memory cells, decide a voltage number according to the storage information, read the at least one of the memory cells according to a plurality of second read voltages matching the voltage number to obtain a plurality of second verification bits, and execute a first soft bit mode decoding procedure according to the second verification bits.

8. The memory storage device of claim 7, wherein the memory controlling circuit unit is further configured to determine whether a second valid codeword is generated by the first soft bit mode decoding procedure,

if the second valid codeword is not generated by the first soft bit mode decoding procedure, the memory controlling circuit unit is configured to increase the voltage number, read the at least one of the memory cells according to a plurality of third read voltages matching the increased voltage number to obtain a plurality of third verification bits, and execute a second soft bit mode decoding procedure according to the third verification bits.

9. The memory storage device of claim 7, wherein data is stored in the at least one of the memory cells, and the operation of memory controlling circuit unit deciding the voltage number according to the storage information comprises:

the memory controlling circuit unit estimates an amount of error bits in the data according to the storage information, wherein the voltage number positively correlates the amount of the error bits in the data.

10. The memory storage device of claim 7, wherein the storage information comprises a number of erased times of the at least one of the memory cells.

11. The memory storage device of claim 7, wherein data is stored in the at least one of the memory cells, and the storage information comprises an elapsed time after storing the data in the at least one of the memory cells.

12. The memory storage device of claim 7, wherein data is stored in the at least one of the memory cells, and the storage information comprises a number of read times of the data stored in the at least one of the memory cells.

13. A memory controlling circuit unit, for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory controlling circuit unit comprises:

a host interface configured to couple to a host system;

a memory interface configured to couple to the rewritable non-volatile memory module;

a memory management circuit coupled to the host interface and the memory interface, and configured to read at least one of the memory cells according to a first read voltage to obtain at least one first verification bit; and

an error checking and correcting circuit, configured to execute a hard bit mode decoding procedure according to the at least one first verification bit, and determine whether a first valid codeword is generated by the hard bit mode decoding procedure,

wherein if the first valid codeword is not generated by the hard bit mode decoding procedure, the memory management circuit is configured to obtain storage information of the at least one of the memory cells, decide a voltage number according to the storage information, read the at least one of the memory cells according to a plurality of second read voltages matching the voltage number to obtain a plurality of second verification bits,

wherein the error checking and correcting circuit is configured to execute a first soft bit mode decoding procedure according to the second verification bits.

14. The memory controlling circuit unit of claim 13, wherein the error checking and correcting circuit is further configured to determine whether a second valid codeword is generated by the first soft bit mode decoding procedure,

if the second valid codeword is not generated by the first soft bit mode decoding procedure, the memory management circuit is configured to increase the voltage number, and read the at least one of the memory cells according to a plurality of third read voltages matching the increased voltage number to obtain a plurality of third verification bits,

wherein the error checking and correcting circuit is further configured to execute a second soft bit mode decoding procedure according to the third verification bits.

15. The memory controlling circuit unit of claim 13, wherein data is stored in the at least one of the memory cells, and the operation of memory management circuit deciding the voltage number according to the storage information comprises:

the memory management circuit estimates an amount of error bits in the data according to the storage information, wherein the voltage number positively correlates the amount of the error bits in the data.

16. The memory controlling circuit unit of claim 13, wherein the storage information comprises a number of erased times of the at least one of the memory cells.

17. The memory controlling circuit unit of claim 13, wherein data is stored in the at least one of the memory cells, and the storage information comprises an elapsed time after storing the data in the at least one of the memory cells.

18. The memory controlling circuit unit of claim 13, wherein data is stored in the at least one of the memory cells, and the storage information comprises a number of read times of the data stored in the at least one of the memory cells.