Data storage device and error correction method thereof

• US 9,274,893 B2
• Filed: 05/07/2014
• Issued: 03/01/2016
• Est. Priority Date: 05/31/2013
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Chen, Chun-Yi
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US14/271,928
• Publication Number:
  US 20140359346A1
• Time in Patent Office: 664 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

The present invention provides a data storage device including a flash memory and a controller. The flash memory is capable of operating in a SLC mode and a non-SLC mode. The controller is configured to perform a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host, and perform an adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to enable the flash memory to operate in the non-SLC mode in the adjustable read operation, and write logic 1 into a most-significant-bit page corresponding to the first word line in the non-SLC mode to adjust voltage distribution of the first page.

Claims

1. A data storage device, comprising:

a flash memory, capable of operating in a SLC mode and a non-SLC mode; and

a controller, configured to perform a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host, and perform an adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to enable the flash memory to operate in the non-SLC mode in the adjustable read operation, and write logic 1 into a most-significant-bit page corresponding to the first word line in the non-SLC mode to adjust voltage distribution of the first page.

2. The data storage device as claimed in claim 1, wherein the non-SLC mode is a MLC mode.

3. The data storage device as claimed in claim 2, wherein the controller is further configured to enable the flash memory to operate in the SLC mode and perform a second read operation to read the page corresponding to the first word line in the SLC mode again after writing the logic 1 into the most-significant-bit page during the adjustable read operation.

4. The data storage device as claimed in claim 3, wherein the controller is further configured to mark the page corresponding to the first word line as a bad page when data read by the second read operation cannot be recovered by coding.

5. The data storage device as claimed in claim 1, wherein the non-SLC mode is a TLC mode.

6. The data storage device as claimed in claim 5, wherein the controller is further configured to write a logic 1 into a central-significant-bit page corresponding to the first word line in the TLC mode during the adjustable read operation to adjust voltage distribution of the memory cell corresponding to the first word line.

7. The data storage device as claimed in claim 6, wherein the controller is further configured to enable the flash memory to operate in the SLC mode and perform a second read operation to read the page corresponding to the first word line in the SLC mode again after writing the logic 1 into the most-significant-bit page and the central-significant-bit page during the adjustable read operation.

8. The data storage device as claimed in claim 7, wherein the controller is further configured to mark the page corresponding to the first word line as a bad page when data read by the second read operation cannot be recovered by coding.

9. The data storage device as claimed in claim 5, wherein the controller is further configured to perform a second read operation to read the page corresponding to the first word line by the read voltage corresponding to the voltage value on the register and increase a read retry count by 1 in the read retry procedure.

10. The data storage device as claimed in claim 9, wherein the controller is further configured to determine whether the read retry count is higher than a first predetermined number in the read retry procedure and perform the adjustable read operation when the read retry count is higher than the first predetermined number.

11. The data storage device as claimed in claim 1, wherein the controller is further configured to perform a read retry procedure before the adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the controller is configured to set voltage value on a register according to a read retry table and have the voltage value of the register serve as read voltage of the flash memory in the read retry procedure.

12. A error correction method, applied to a data storage device, wherein the data storage device comprises a flash memory capable of operating in a SLC mode and a non-SLC mode, the error correction method comprising:

performing a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host;

determining whether data read by the first read operation can be recovered by coding; and

performing an adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the adjustable read operation comprises;

enabling the flash memory to operate in the non-SLC mode; and

writing logic 1 into a most-significant-bit page corresponding to the first word line in the non-SLC mode to adjust voltage distribution of the first page.

13. The error correction method as claimed in claim 12, wherein the non-SLC mode is a MLC mode.

14. The error correction method as claimed in claim 13, wherein the step of the adjustable read operation further comprises:

enabling the flash memory to operate in the SLC mode after writing the logic 1 into the most-significant-bit page; and

performing a second read operation to read the page corresponding to the first word line in the SLC mode again.

15. The error correction method as claimed in claim 14, wherein the step of the adjustable read operation further comprises marking the page corresponding to the first word line as a bad page when data read by the second read operation cannot be recovered by coding.

16. The error correction method as claimed in claim 12, wherein the non-SLC mode is a TLC mode.

17. The error correction method as claimed in claim 16, wherein the step of the adjustable read operation further comprises writing a logic 1 into a central-significant-bit page corresponding to the first word line in the TLC mode to adjust voltage distribution of memory cell corresponding to the first word line.

18. The error correction method as claimed in claim 17, wherein the step of the adjustable read operation further comprises:

enabling the flash memory to operate in the SLC mode after writing the logic 1 into the most-significant-bit page and the central-significant-bit page; and

performing a second read operation to read the page corresponding to the first word line in the SLC mode again.

19. The error correction method as claimed in claim 18, wherein the step of the adjustable read operation further comprises marking the page corresponding to the first word line as a bad page when data read by the second read operation cannot be recovered by coding.

20. The error correction method as claimed in claim 12, further comprising performing a read retry procedure before the adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the read retry procedure comprises setting voltage value on a register according to a read retry table and having the voltage value of the register serve as read voltage of the flash memory.

21. The error correction method as claimed in claim 20, wherein the step of the read retry procedure further comprises performing a second read operation to read the page corresponding to the first word line by the read voltage corresponding to the voltage value on the register and increasing a read retry count by 1.

22. The error correction method as claimed in claim 21, wherein the step of the read retry procedure further comprises:

determining whether the read retry count is higher than a first predetermined number in the read retry procedure; and

performing the adjustable read operation when the read retry count is higher than the first predetermined number.

23. A data reading method, applied to a data storage device, wherein the data storage device comprises a flash memory capable of operating in a SLC mode and a multi-level cell mode, the data reading method comprising:

performing a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host to obtain a first data segment;

enabling the flash memory to operate in the multi-level cell mode when the first data segment cannot be recovered by coding; and

writing a predetermined data into a most-significant-bit page corresponding to the first word line in the multi-level cell mode;

enabling the flash memory to operate in the SLC mode; and

reading the page corresponding to the first word line again to obtain a second data segment.

24. The data reading method as claimed in claim 23, wherein the predetermined data is 0xFF.

25. The data reading method as claimed in claim 23, further comprising:

transmitting the second data segment to the host when the second data segment can be recovered by coding.

26. The data reading method as claimed in claim 23, further comprising:

marking the page corresponding to the first word line as a bad page when the second data segment cannot be recovered by coding.

27. The data reading method as claimed in claim 23, further comprising:

marking a first block corresponding to the first word line as a bad block when the second data segment cannot be recovered by coding.

28. A data reading method, applied to a data storage device, wherein the data storage device comprises a flash memory capable of operating in a SLC mode and a multi-level cell mode, the data reading method comprising:

performing a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host to obtain a first data segment;

writing a predetermined data into a most-significant-bit page corresponding to the first word line in the multi-level cell mode when the first data segment cannot be recovered by coding;

enabling the flash memory to operate in the multi-level cell mode when the first data segment cannot be recovered by coding;

writing a predetermined data into a most-significant-bit page corresponding to the first word line in the multi-level cell mode;

reading the page corresponding to the first word line in the SLC mode again to obtain a second data segment; and

transmitting the second data segment to the host when the second data segment can be recovered by coding.