Memory hub architecture having programmable lane widths

• US 9,274,991 B2
• Filed: 06/10/2014
• Issued: 03/01/2016
• Est. Priority Date: 03/08/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jobs, Jeffrey R., Stenglein, Thomas A.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US14/300,903
• Publication Number:
  US 20140297974A1
• Time in Patent Office: 630 Days
• Field of Search: 711/170, 710/27, 710/307, 710/300
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Claims

1. An apparatus comprising:

a plurality of memory devices;

logic coupled to the plurality of memory devices and configured to route memory requests to, and responses from, the plurality of memory devices;

an upstream bus coupled to the logic and having a width of M bits; and

a downstream bus coupled to the logic and having a width of N bits,

wherein the sum of M and N is fixed and values of M and N are adjustable.

2. The apparatus of claim 1, wherein the logic comprises a memory hub.

3. The apparatus of claim 1, further comprising a processor coupled to the logic through the upstream and downstream buses.

4. The apparatus of claim 3, wherein the processor is coupled to the logic through a system controller.

5. The apparatus of claim 4, wherein the system controller includes a memory hub controller.

6. The apparatus of claim 1, wherein the plurality of memory devices and the logic are included in a memory module.

7. The apparatus of claim 1, wherein the plurality of memory devices comprises a first plurality of memory devices, the logic comprises first logic, the upstream bus comprises a first upstream bus and the downstream bus comprises a first downstream bus, the apparatus further comprising:

a second plurality of memory devices;

second logic coupled to the second plurality of memory devices and configured to route memory requests to, and responses from, the second plurality of memory devices;

a second upstream bus coupled between the first logic and the second logic; and

a second downstream bus coupled between the first logic and the second logic.

8. The apparatus of claim 1 wherein the values of M and N are adjustable during operation of the apparatus.

9. The apparatus of claim 1, wherein the logic is coupled to the plurality of memory devices through command, address and data buses.

10. The apparatus of claim 1, wherein each of the buses is configured to carry packets that include a header and data.

11. The apparatus of claim 10, wherein the logic is configured to process a received memory request without interaction with an external controller.

12. The apparatus of claim 1, wherein the values of M and N are adjustable while the apparatus is being initialized.

13. The apparatus of claim 1, wherein the values of M and N depend on a magnitude of actual signal flow to the logic.

14. The apparatus of claim 1, wherein the values of M and N depend on a magnitude of expected signal flow to the logic.

15. The apparatus of claim 1, wherein the values of M and N depend on a nature of actual memory accesses.

16. The apparatus of claim 1, wherein the values of M and N depend on a nature of expected memory accesses.

17. The apparatus of claim 1, wherein the values of M and N dynamically change based on actual traffic flow through the buses.

18. The apparatus of claim 17, wherein the logic is configured to determine the actual traffic flow through the buses.

19. The apparatus of claim 1, wherein the logic is configured to adjust the values of M and N responsive to receiving configuration data.

20. The apparatus of claim 1, wherein the logic is configured to adjust M and N by configuring buffers coupled to the buses as either input buffers or output buffers.

21. The apparatus of claim 1, wherein the values of M and N dynamically change based on anticipated traffic flow through the buses.

22. The apparatus of claim 21, wherein the anticipated traffic flow is determined by a user of the apparatus.

23. The apparatus of claim 1, wherein the values of M and N are based on a type of application program being executed by a processor coupled to the logic through the buses.

24. The apparatus of claim 1, wherein the buses include bi-directional signal lines.

25. The apparatus of claim 1, wherein the buses include some unidirectional signal lines.

26. An apparatus comprising:

a plurality of memory devices;

logic coupled to the plurality of memory devices and configured to route memory requests to, and responses from, the plurality of memory devices;

an upstream bus coupled to the logic and having a width of M bits; and

a downstream bus coupled to the logic and having a width of N bits,

wherein the sum of M and N is fixed, values of M and N are adjustable, and wherein the values of M and N depend on a nature of expected memory accesses.

27. An apparatus comprising:

a plurality of memory devices;

logic coupled to the plurality of memory devices and configured to route memory requests to, and responses from, the plurality of memory devices;

an upstream bus coupled to the logic and having a width of M bits; and

a downstream bus coupled to the logic and having a width of N bits,

wherein the sum of M and N is fixed, values of M and N are adjustable, and wherein the values of M and N dynamically change based on actual traffic flow through the buses.