Apparatus and method for aiding in designing electronic circuits

• US 9,275,183 B2
• Filed: 07/08/2014
• Issued: 03/01/2016
• Est. Priority Date: 07/28/2011
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ohtsuka, Ikuo, Sakata, Toshiyasu
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US14/325,405
• Publication Number:
  US 20140325469A1
• Time in Patent Office: 602 Days
• Field of Search: 716/100, 716/112, 716/113, 716/118, 716/126, 716/129, 716/132, 716/137
• US Class Current: 1/1
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H05K 3/0005 for designing circuits by computer

Abstract

First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit.

Claims

1. A circuit design aiding apparatus comprising:

a memory configured to store information about a first pin group to be wired to a second pin group, the information including logical connection data for wiring of pins in the first pin group; and

a processor configured to perform a procedure including;

selecting a set of pair candidates each specifying a pair of pins in the first pin group, wherein distance between the pins of each pair candidate is within a specified range,

determining which pins in the first pin group are to be wired in pairs, based on the selected set of pair candidates, and

assigning the logical connection data to pins in the second pin group, depending on the pin pairs chosen from the first pin group, so that the pins in the first pin group are to be wired to the pins in the second pin group according to the assigned logical connection data, wherein;

two pair candidates are said to be adjacent when the two pair candidates share a pin in the first pin group, and

the determining includes producing a graph whose nodes respectively represent the pair candidates in the selected set and whose edges represent adjacency of the pair candidates in the selected set, choosing a first node in preference to a second node in the produced graph when a smaller number of edges extend from the first node than from the second node, and determining that the pair of pins in the pair candidate represented by the chosen first node be wired in a pair.

2. The circuit design aiding apparatus according to claim 1, wherein the determining includes removing the chosen first node, as well as the edges extending therefrom, from the graph.

3. The circuit design aiding apparatus according to claim 1, wherein the determining chooses the first node in preference to the second node when the first and second nodes are equal in the number of edges, but the first node has a smaller distance of pins than the second node.

4. The circuit design aiding apparatus according to claim 3, wherein:

the determining includes calculating a total distance related to a specific node by adding up the distances of pins for all the nodes, except the specific node, that share a common pin with the specific node;

the determining executes the calculating of the total distance for each of the first and second nodes when the first and second nodes are equal in both the number of edges and the distance of pins; and

the determining chooses the first node in preference to the second node when the first node has a larger total distance than the second node.

5. The circuit design aiding apparatus according to claim 4, wherein:

the determining chooses pairs of pins in the first pin group by repeating;

newly choosing one of the nodes in the graph, and

removing the chosen node, as well as the edges extending therefrom, from the graph;

the determining calculates, for each of the first and second nodes, the number of edges, inclusive of the removed edges to the nodes that have been chosen, when the first and second nodes are equal in the total distance; and

the determining chooses the first node in preference to the second node when the first node has a smaller number of edges than the second node.

6. The circuit design aiding apparatus according to claim 1, wherein:

the pins in the first and second pin groups are each given an identifier indicating a category of signals assigned thereto; and

the selecting selects each pair candidate by combining two pins having the same identifier.

7. The circuit design aiding apparatus according to claim 6, wherein the selecting selects pair candidates by using a factor that is determined from a combination of the identifiers of two pins, the factor indicating likelihood that the two pins are chosen to be wired in a pair.

8. A circuit design aiding method, comprising:

selecting, by a processor, a set of pair candidates each specifying a pair of pins in a first pin group to be wired to a second pin group, by consulting information about the first pin group to find two pins whose distance is within a specified range, the information including logical connection data for wiring of pins in the first pin group;

determining, by the processor, which pins in the first pin group are to be wired in pairs, based on the selected set of pair candidates; and

assigning, by the processor, the logical connection data to pins in the second pin group, depending on the pin pairs chosen from the first pin group, so that the pins in the first pin group are to be wired to the pins in the second pin group according to the assigned logical connection data, wherein;

two pair candidates are said to be adjacent when the two pair candidates share a pin in the first pin group, and

the determining includes producing a graph whose nodes respectively represent the pair candidates in the selected set and whose edges represent adjacency of the pair candidates in the selected set, choosing a first node in preference to a second node in the produced graph when a smaller number of edges extend from the first node than from the second node, and determining that the pair of pins in the pair candidate represented by the chosen first node be wired in a pair.

9. A non-transitory computer-readable storage medium storing a program that causes a computer to perform a procedure comprising:

selecting a set of pair candidates each specifying a pair of pins in a first pin group to be wired to a second pin group, by consulting information about the first pin group to find two pins whose distance is within a specified range, the information including logical connection data for wiring of pins in the first pin group;

determining which pins in the first pin group are to be wired in pairs, based on the selected set of pair candidates; and

assigning the logical connection data to pins in the second pin group, depending on the pin pairs chosen from the first pin group, so that the pins in the first pin group are to be wired to the pins in the second pin group according to the assigned logical connection data, wherein;

two pair candidates are said to be adjacent when the two pair candidates share a pin in the first pin group, and

the determining includes producing a graph whose nodes respectively represent the pair candidates in the selected set and whose edges represent adjacency of the pair candidates in the selected set, choosing a first node in preference to a second node in the produced graph when a smaller number of edges extend from the first node than from the second node, and determining that the pair of pins in the pair candidate represented by the chosen first node be wired in a pair.