Power management in an electronic system through reducing energy usage of a battery and/or controlling an output power of an amplifier thereof

• US 9,275,690 B2
• Filed: 05/30/2012
• Issued: 03/01/2016
• Est. Priority Date: 05/30/2012
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Tahoe RF Semiconductor, Inc. (Renesas Electronics Corporation)
• Inventors: Shaw, Michael Joseph, Schiller, Christopher T
• Primary Examiner(s): NGUYEN, HIEN N
• Application Number:
  US13/483,151
• Publication Number:
  US 20130322197A1
• Time in Patent Office: 1,371 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

A method includes forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array including N amplifier stages in parallel to each other, with N>1. The method also includes coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array, and controlling an output power of the power control circuit by switching one or more appropriate gate switches of the gate switch array to apply an input signal from the buffer stage to a corresponding one or more amplifier stages coupled to the one or more appropriate gate switches such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.

Claims

1. A method comprising:

forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array comprising N amplifier stages in parallel to each other, N>

1;

coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array; and

controlling an output power of the power control circuit by switching at least one appropriate gate switch of the gate switch array to apply an input signal from the buffer stage to a corresponding at least one amplifier stage coupled to the at least one appropriate gate switch such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.

2. The method of claim 1, further comprising providing an NMOS common source amplifier bank as the amplifier array.

3. The method of claim 2, further comprising coupling a lower transistor and a higher transistor to each other in each amplifier stage such that the lower transistor provides for amplification and the higher transistor provides for isolation for the each amplifier stage.

4. A power control circuit comprising:

a buffer stage at an input thereof;

an amplifier array comprising N amplifier stages in parallel to each other, N>

1; and

a gate switch array comprising N gate switches, with each gate switch coupled to a corresponding amplifier stage,

wherein an output power of the power control circuit is configured to be controlled by switching at least one appropriate gate switch of the gate switch array to apply an input signal from the buffer stage to a corresponding at least one amplifier stage coupled to the at least one appropriate gate switch such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.

5. The power control circuit of claim 4, wherein each amplifier stage comprises:

a lower transistor coupled to a higher transistor such that the lower transistor provides for amplification and the higher transistor provides for isolation for the amplifier stage.

6. The power control circuit of claim 4, wherein the each gate switch comprises:

a through switch coupled between the buffer stage and an amplifier stage to apply the input signal to the amplifier stage upon closure thereof; and

a ground switch coupled between the amplifier stage and a ground voltage terminal to turn off the amplifier stage upon closure thereof.

7. The power control circuit of claim 6, wherein the ground switch is open when the input signal is applied to the amplifier stage.