Power management in an electronic system through reducing energy usage of a battery and/or controlling an output power of an amplifier thereof
First Claim
1. A method comprising:
- forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array comprising N amplifier stages in parallel to each other, N>
1;
coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array; and
controlling an output power of the power control circuit by switching at least one appropriate gate switch of the gate switch array to apply an input signal from the buffer stage to a corresponding at least one amplifier stage coupled to the at least one appropriate gate switch such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.
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Accused Products
Abstract
A method includes forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array including N amplifier stages in parallel to each other, with N>1. The method also includes coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array, and controlling an output power of the power control circuit by switching one or more appropriate gate switches of the gate switch array to apply an input signal from the buffer stage to a corresponding one or more amplifier stages coupled to the one or more appropriate gate switches such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.
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Citations
7 Claims
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1. A method comprising:
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forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array comprising N amplifier stages in parallel to each other, N>
1;coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array; and controlling an output power of the power control circuit by switching at least one appropriate gate switch of the gate switch array to apply an input signal from the buffer stage to a corresponding at least one amplifier stage coupled to the at least one appropriate gate switch such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on. - View Dependent Claims (2, 3)
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4. A power control circuit comprising:
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a buffer stage at an input thereof; an amplifier array comprising N amplifier stages in parallel to each other, N>
1; anda gate switch array comprising N gate switches, with each gate switch coupled to a corresponding amplifier stage, wherein an output power of the power control circuit is configured to be controlled by switching at least one appropriate gate switch of the gate switch array to apply an input signal from the buffer stage to a corresponding at least one amplifier stage coupled to the at least one appropriate gate switch such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on. - View Dependent Claims (5, 6, 7)
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Specification