Driver and memory controller having the same
First Claim
Patent Images
1. A bus line driver comprising:
- a first NMOS transistor connected between a ground voltage source and a first node, and controlled by a first signal;
a second NMOS transistor connected between the first node and a second node, and controlled by a second signal;
a first PMOS transistor connected between the second node and a power supply voltage source, and controlled by a third signal; and
a pad connected to the first node,wherein, when a first transmission method is supported and the first PMOS transistor is activated, the power supply voltage is applied to the pad via the second NMOS transistor, andwhen a second transmission method is supported, the pad is connected to the second node.
2 Assignments
0 Petitions
Accused Products
Abstract
A memory controller includes a bus driver that allows the controller to support both a semiconductor memory device supporting a low power double data rate 3 (LPDDR3) transmission method and a semiconductor memory device supporting a low power double data rate 4 (LPDDR4) transmission method.
18 Citations
19 Claims
-
1. A bus line driver comprising:
-
a first NMOS transistor connected between a ground voltage source and a first node, and controlled by a first signal; a second NMOS transistor connected between the first node and a second node, and controlled by a second signal; a first PMOS transistor connected between the second node and a power supply voltage source, and controlled by a third signal; and a pad connected to the first node, wherein, when a first transmission method is supported and the first PMOS transistor is activated, the power supply voltage is applied to the pad via the second NMOS transistor, and when a second transmission method is supported, the pad is connected to the second node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A memory controller comprising:
-
a driver configured to transmit data to a semiconductor memory device supporting a first or second transmission method; and a data bus connected to the driver, and configured to transmit the data to and receive the data from the semiconductor memory device, wherein the driver comprises; a first NMOS transistor connected between a ground voltage source and a first node, and controlled by a first signal; a second NMOS transistor connected between the first node and a second node, and controlled by a second signal; a first PMOS transistor connected between the second node and a power supply voltage source, and controlled by a third signal; and a pad connected to the first node, wherein, when the first transmission method is supported and the first PMOS transistor is activated, a power supply voltage is applied to the pad via the second node, and when the second transmission method is supported, the pad is connected to the second node. - View Dependent Claims (14, 15)
-
-
16. An electronic apparatus, comprising:
-
a line driver including circuitry for low power double data rate 3 (LPDDR3) transmission; circuitry for low power double data rate 4 (LPDDR4) transmission; and selection circuitry for selecting between LPDDR3 and LPDDR4 transmission, wherein the selection circuitry includes an antifuse. - View Dependent Claims (17, 18, 19)
-
Specification