Differential vector storage for dynamic random access memory

• US 9,275,720 B2
• Filed: 03/15/2013
• Issued: 03/01/2016
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Cronie, Harm, Shokrollahi, Amin
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/843,785
• Publication Number:
  US 20140063915A1
• Time in Patent Office: 1,082 Days
• Field of Search: 365/149
• US Class Current: 1/1
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 7/20 Conversion to or from n-out-of-m codes

Abstract

A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2ⁿ distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.

Claims

1. A system comprising:

a memory area comprising a plurality of cell groups of k memory cells in each cell group, wherein k is an integer greater than one;

row and column decoder circuitry coupled to the memory area and configured to select at least one cell group;

storage data encoder circuitry configured to encode an n-bit value, for an n>

k, received at a data input of the system into a k-entry codeword of a voltage code the k-entry codeword representing a selection of a first permutation vector based on a first half of the n-bit value and a second permutation vector based on a second half of the n-bit value, wherein the first and second permutation vectors are weighted with first and second weights, respectively, and an element-by-element summation of the first and second permutation vectors, wherein each entry in the k entry codeword is one of three possible entry values; and

storage data decoder circuitry configured to reconstruct the n -bit value from a k-entry vector read from the selected cell group by forming a k-length intermediate vector containing information about relative magnitudes of the elements of the read k-entry vector, the k-length intermediate vector determining the second half of the received n-bit value, forming a k-length difference vector by subtracting a weighted version of the first k-length intermediate vector from the read k-entry vector, the k-length difference vector determining the first half of the received n-bit value and outputting the reconstructed n-bit value.

2. The system of claim 1, wherein each of the k entries of k entry codeword can be summed and wherein a sum over the -k- entries of each vector in at least a subset of the set of possible k-entry codewords is equal to a predetermined constant over the subset.

3. The system of claim 1, wherein the system is one of an integrated circuit device, a discrete memory device, or a device having embedded memory.

4. The system of claim 1, wherein the memory cells comprise circuit elements configured to store the k-entry codeword as a plurality of electrical quantities, the codeword selected from a set of at least 2ⁿ distinct possible codewords.

5. The system of claim 4, wherein the electrical quantities are charges on a plurality of capacitors.

6. The system of claim 1, wherein the storage data encoder circuitry is configured to form a first set of permutation selection quantities from the first half of the received n bit value and a second set of permutation selection quantities from the second half of the received n bit value.

7. The system of claim 6, wherein the storage data encoder circuitry comprises a logic circuit configured to implement Boolean algebra to form the first and second sets of permutation selection quantities.

8. The system of claim 1, wherein the storage data encoder circuitry processes the first half of the n-bit value and the second half of the n-bit value to identify indices of the first and second permutation vectors, respectively.

9. The system of claim 1, wherein the storage data decoder circuitry is configured to form k-length intermediate vectors comprising either (i) vectors having a logic 1 in positions corresponding to positions of the read k-entry vector having the largest values and logic zeros in other positions, or (ii) vectors having ordered magnitude indicators in positions corresponding to positions of the read k-entry vector having the largest values and logic zeros in other positions.

10. The system of claim 1, wherein the storage data decoder circuitry is configured to determine the second half of the n-bit value by either (i) forming quantities that are Boolean functions of the intermediate vector and using the quantities to determine the second half of the n-bit value or (ii) identifying indices of larger magnitude entries that are Boolean functions of the second half of the n information bits.

11. The system of claim 1, wherein the storage data decoder circuitry is configured to determine the first half of the n-bit value by (i) forming quantities that are Boolean functions of the intermediate vector to determine the bits or (ii) using Boolean functions of the n/2 bits that correspond to indices of entries having the highest magnitudes.

12. The system of claim 1 wherein the storage data decoder circuitry is configured to use weights based on at least one system parameter selected from the group consisting of a refreshed interval parameter, a decay time constant parameter, and a process variation parameter.

13. A method comprising:

receiving a set of n information bits;

determining a first k-length vector having a first weighting factor from a first n/2 bits representing a first half of the set of received n information bits;

determining a second k-length vector having a second weighting factor from a second n/2 bits representing a second half of the set of received n information bits;

combining the respective elements of the first k-length vector and the second k-length vector to form a k-length codeword, wherein the k-length codeword contains multiple elements, each element selected from a set of at least three values;

selecting a group of memory cells within a memory area based on a received set of address selection signals, each memory cell comprising at least one circuit element capable of storing an electrical quantity; and

,

storing each element of the k-length codeword within the corresponding memory cell within the selected group of memory cells.

14. The method of claim 13 wherein the first k-length vector is formed based on a first set of quantities determined from the first n/2 bits, and the second k-length vector is formed based on a second set of quantities determined from the second n/2 bits.

15. The method of claim 13 wherein the first k-length vector is a permutation vector selected based on the first n/2 bits, and the second k-length vector is a permutation vector based on the second n/2 bits.

16. The method of claim 13 wherein the first set of quantities and the second set of quantities are formed using the same Boolean operations.

17. The method of claim 13 wherein a plurality of elements of the first k-length vector are weighted values of the first n/2 bits when the first set of quantities correspond to one predetermined set of a plurality of predetermined sets.

18. The method of claim 13 wherein a plurality of elements of the second k-length vector are weighted values of the second n/2 bits when the second set quantities correspond to one predetermined set of a plurality of predetermined sets.

19. The method of claim 13 wherein the first weighting factor and the second weighting factor are selected based in part on at least one parameter from the group consisting of a refresh interval parameter, a decay time constant parameter, and a process variation parameter.

20. A method comprising:

receiving a k-length read observation vector representing a set of n information bits having k entries, each entry having a corresponding magnitude;

determining a first k-length Boolean vector based on the magnitudes of the k entries;

determining a second n/2 bits of an n-bit data vector based on the first k-length Boolean vector;

determining a second k-length Boolean vector based on an intermediate difference vector formed by subtracting, element-by-element, a weighted version of the first k-length Boolean vector from the k-length observation vector;

determining a first n/2 bits of the n-bit data vector based on the second k-length Boolean vector; and

,

recovering the n set of information bits by appending the second n/2 bits to the end of the first n/2 bits.