Differential vector storage for dynamic random access memory
First Claim
1. A system comprising:
- a memory area comprising a plurality of cell groups of k memory cells in each cell group, wherein k is an integer greater than one;
row and column decoder circuitry coupled to the memory area and configured to select at least one cell group;
storage data encoder circuitry configured to encode an n-bit value, for an n>
k, received at a data input of the system into a k-entry codeword of a voltage code the k-entry codeword representing a selection of a first permutation vector based on a first half of the n-bit value and a second permutation vector based on a second half of the n-bit value, wherein the first and second permutation vectors are weighted with first and second weights, respectively, and an element-by-element summation of the first and second permutation vectors, wherein each entry in the k entry codeword is one of three possible entry values; and
storage data decoder circuitry configured to reconstruct the n -bit value from a k-entry vector read from the selected cell group by forming a k-length intermediate vector containing information about relative magnitudes of the elements of the read k-entry vector, the k-length intermediate vector determining the second half of the received n-bit value, forming a k-length difference vector by subtracting a weighted version of the first k-length intermediate vector from the read k-entry vector, the k-length difference vector determining the first half of the received n-bit value and outputting the reconstructed n-bit value.
2 Assignments
0 Petitions
Accused Products
Abstract
A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.
-
Citations
20 Claims
-
1. A system comprising:
-
a memory area comprising a plurality of cell groups of k memory cells in each cell group, wherein k is an integer greater than one; row and column decoder circuitry coupled to the memory area and configured to select at least one cell group; storage data encoder circuitry configured to encode an n-bit value, for an n>
k, received at a data input of the system into a k-entry codeword of a voltage code the k-entry codeword representing a selection of a first permutation vector based on a first half of the n-bit value and a second permutation vector based on a second half of the n-bit value, wherein the first and second permutation vectors are weighted with first and second weights, respectively, and an element-by-element summation of the first and second permutation vectors, wherein each entry in the k entry codeword is one of three possible entry values; andstorage data decoder circuitry configured to reconstruct the n -bit value from a k-entry vector read from the selected cell group by forming a k-length intermediate vector containing information about relative magnitudes of the elements of the read k-entry vector, the k-length intermediate vector determining the second half of the received n-bit value, forming a k-length difference vector by subtracting a weighted version of the first k-length intermediate vector from the read k-entry vector, the k-length difference vector determining the first half of the received n-bit value and outputting the reconstructed n-bit value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method comprising:
-
receiving a set of n information bits; determining a first k-length vector having a first weighting factor from a first n/2 bits representing a first half of the set of received n information bits; determining a second k-length vector having a second weighting factor from a second n/2 bits representing a second half of the set of received n information bits; combining the respective elements of the first k-length vector and the second k-length vector to form a k-length codeword, wherein the k-length codeword contains multiple elements, each element selected from a set of at least three values; selecting a group of memory cells within a memory area based on a received set of address selection signals, each memory cell comprising at least one circuit element capable of storing an electrical quantity; and
,storing each element of the k-length codeword within the corresponding memory cell within the selected group of memory cells. - View Dependent Claims (14, 15, 16, 17, 18, 19)
-
-
20. A method comprising:
-
receiving a k-length read observation vector representing a set of n information bits having k entries, each entry having a corresponding magnitude; determining a first k-length Boolean vector based on the magnitudes of the k entries; determining a second n/2 bits of an n-bit data vector based on the first k-length Boolean vector; determining a second k-length Boolean vector based on an intermediate difference vector formed by subtracting, element-by-element, a weighted version of the first k-length Boolean vector from the k-length observation vector; determining a first n/2 bits of the n-bit data vector based on the second k-length Boolean vector; and
,recovering the n set of information bits by appending the second n/2 bits to the end of the first n/2 bits.
-
Specification