Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

• US 9,275,723 B2
• Filed: 04/10/2014
• Issued: 03/01/2016
• Est. Priority Date: 04/10/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Garbowski, Leigh
• Application Number:
  US14/250,370
• Publication Number:
  US 20140307501A1
• Time in Patent Office: 691 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/337 Design optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Claims

1. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising:

a floating body memory cell comprising;

a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types;

a first region in electrical contact with said floating body region;

said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type;

a second transistor connected to said second region of said floating body memory cell; and

a third transistor connected to said second transistor.

2. The floating body SRAM cell of claim 1, said floating body memory cell further comprising:

a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region having said first conductivity type.

3. The floating body SRAM cell of claim 2, further comprising:

a first gate positioned between said first and second regions; and

a second gate positioned between said first and third regions.

4. The floating body SRAM cell of claim 2, wherein:

said second transistor functions as a pull down device and said second transistor is gated by said third transistor; and

a write access transistor is connected to said third region.

5. The floating body SRAM cell of claim 1, wherein said second region has multiple contacts electrically connected thereto.

6. The floating body SRAM cell of claim 1, wherein said floating body memory cell further comprises:

a gate positioned between said first and second regions.

7. The floating body SRAM cell of claim 1, wherein said second transistor functions as a pull down device and said second transistor is gated by said third transistor.

8. The floating body SRAM cell of claim 1, said floating body memory cell further comprising:

a third region in electrical contact with said floating body region and spaced apart from said first and second regions, said third region having said first conductivity type; and

a fourth transistor electrically connected to said third region.

9. The floating body SRAM cell of claim 1, further comprising:

a fourth transistor electrically connected to said third region.

10. The floating body SRAM cell of claim 1, wherein said first region is grounded.

11. The floating body SRAM cell of claim 1, wherein said floating body SRAM cell is used as a dual port SRAM cell.

12. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising:

a floating body memory cell comprising;

a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types;

a first region in electrical contact with said floating body region;

said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type;

a pull down device having a gate electrically connected to said second region; and

a select device electrically connected to said pull down device, said select device being configured to be connected to a read bit line.

13. The floating body SRAM cell of claim 12, wherein said select device is connected to said read bit line and said read bit line is pre-charged such that a state of said floating body region can be read according to whether said read bit line is pulled down when said select device is enabled;

wherein if said state of said floating body region is “

1”

, said pull down device is turned on and when said select device is enabled, said read bit line is pulled down.

14. The floating body SRAM cell of claim 13, wherein said read bit line has an output of either zero volts or a pre-charged voltage level, depending upon whether said floating body region is in state “

1”

or state “

0”

.

15. The floating body SRAM cell of claim 12, wherein said first region is electrically connected to a write bit line, and said floating body memory cell includes a gate positioned between said first and second regions;

wherein a write operation to said floating body region is performable through said write bit line in conjunction with a predetermined bias on said gate.

16. The floating body SRAM cell of claim 12, wherein said first region is grounded;

said SRAM cell further comprising;

a write device connecting a write word line to said second region;

wherein pure logic levels are used to read from and write to said floating body region, and enablement of said write device overpowers said floating body region to write to said floating body region.

17. The floating body SRAM cell of claim 16, further comprising:

a write bit line electrically connected to said write device;

said write bit line being separate and independently operable of said read bit line to allow for dual port functionality.

18. The floating body SRAM cell of claim 12, further comprising a write access transistor connected between a write bit line and said first region.