Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers
First Claim
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1. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising:
- a floating body memory cell comprising;
a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types;
a first region in electrical contact with said floating body region;
said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;
a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type;
a second transistor connected to said second region of said floating body memory cell; and
a third transistor connected to said second transistor.
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Abstract
A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.
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Citations
18 Claims
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1. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising:
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a floating body memory cell comprising; a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types; a first region in electrical contact with said floating body region;
said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type; a second transistor connected to said second region of said floating body memory cell; and a third transistor connected to said second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays, said cell comprising:
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a floating body memory cell comprising; a floating body region configured to be charged to a level indicative of a state of the memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types; a first region in electrical contact with said floating body region;
said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; anda second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type; a pull down device having a gate electrically connected to said second region; and a select device electrically connected to said pull down device, said select device being configured to be connected to a read bit line. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification