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Temperature compensation management in solid-state memory

  • US 9,275,741 B1
  • Filed: 09/10/2014
  • Issued: 03/01/2016
  • Est. Priority Date: 09/10/2014
  • Status: Active Grant
First Claim
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1. A data storage device comprising:

  • a non-volatile memory array including a plurality of non-volatile memory cells; and

    a controller configured to;

    receive a signal indicating a temperature of at least a portion of the data storage device;

    determine a first offset program verify level associated with a first programming level based at least in part on the temperature;

    determine a second offset program verify level associated with a second programming level based at least in part on the temperature;

    program a first set of the memory cells of the non-volatile memory array using the first offset program verify level; and

    program a second set of the memory cells of the non-volatile memory array using the second offset program verify level;

    wherein the first and second offset program verify levels are determined to provide more even distribution of programming levels, thereby reducing an overall bit error rate associated with the non-volatile memory array.

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