Method of fabricating semiconductor device

• US 9,275,863 B2
• Filed: 09/22/2014
• Issued: 03/01/2016
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Numazawa, Sumito, Nakazawa, Yoshito, Kobayashi, Masayoshi, Kudo, Satoshi, Imai, Yasuo, Kubo, Sakae, Shigematsu, Takashi, Ohnishi, Akihiro, Uesawa, Kozo, Oishi, Kentaro
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US14/492,382
• Publication Number:
  US 20150011081A1
• Time in Patent Office: 526 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A method of manufacturing a semiconductor device including a MISFET, comprising steps of:

(a) forming a first trench in a semiconductor substrate, the first trench including a first portion and a second portion arranged near a top surface of the semiconductor substrate rather than the first portion such that the second portion has a sloping shape rather than first portion;

(b) forming a gate insulating film of the MISFET over the semiconductor substrate including the first trench;

(c) forming a gate electrode of the MISFET over the gate insulating film in order to be embedded in the first trench;

(d) after the step (c), recessing the gate electrode such that an upper surface of the gate electrode is arranged at a position lower than the second portion;

(e) after the step (d), recessing the gate insulating film such that an upper surface of the gate insulating film is arranged at a position lower than the second portion; and

(f) after the step (e), forming a first insulating film over the gate electrode, the gate insulating film, the second portion and the top surface of the semiconductor substrate.

2. The method of manufacturing a semiconductor device according to the claim 1,

wherein, after the step (e), the gate electrode and the gate insulating film are not formed on the second portion.

3. The method of manufacturing a semiconductor device according to the claim 1,

wherein the gate insulating film includes a first gate insulating film formed on the first trench and a second gate insulating film formed between the first gate insulating film and the gate electrode,

wherein the first gate insulating film is formed by a thermal oxidation method, and

wherein the second gate insulating film is formed by a CVD method.