Protrusion bump pads for bond-on-trace processing

• US 9,275,967 B2
• Filed: 01/06/2014
• Issued: 03/01/2016
• Est. Priority Date: 01/06/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Yu-Min, Wu, Jiun-Yi
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US14/148,482
• Publication Number:
  US 20150194404A1
• Time in Patent Office: 785 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11614 by chemical means only
• CPC Class Codes: H01L 2224/11622 Photolithography
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13294 with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
• CPC Class Codes: H01L 2224/133 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/1712 Layout layout of bump connectors prior to the connecting process H01L2224/1412
• CPC Class Codes: H01L 2224/17132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/81424 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81444 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81466 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/0533 : 3rd Group
• CPC Class Codes: H01L 2924/0534 : 4th Group
• CPC Class Codes: H01L 2924/05342 : ZrO2
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/05994 : having an amorphous microstructure, i.e. glass
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1531 : the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/20641 : larger or equal to 100 microns less than 200 microns
• CPC Class Codes: H05K 1/0268 : for electrical inspection or testing
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/0989 : Coating free areas, e.g. areas other than pads or lands free of solder resist
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/0353 : Making conductive layer thin, e.g. by etching selective thinning for providing different thickness H05K2203/0369
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

Claims

1. A method, comprising:

separating a substrate from a carrier on which an additional substrate is formed, wherein the separated substrate comprises a conductive layer on a top surface of the substrate and a plurality of conductive pillars each extending from a bottom surface of the substrate and through the substrate to the conductive layer; and

forming a protrusion bump pad over each of a first subset of the conductive pillars by selectively removing the conductive layer except from over each of the first subset of conductive pillars.

2. The method of claim 1 wherein forming the protrusion bump pad over each of the first subset of the conductive pillars comprises:

forming a photoresist mask on the conductive layer over each of the first subset of conductive pillars but not over the remaining conductive pillars; and

etching to remove the conductive layer except from underneath the photoresist masks.

3. The method of claim 2 wherein forming the photoresist mask on the conductive layer over each of the first subset of conductive pillars but not over the remaining conductive pillars comprises forming the photoresist mask on the conductive layer over each of the first subset of conductive pillars but not over the remaining portions of the conductive layer.

4. The method of claim 2 wherein forming the photoresist mask on the conductive layer over each of the first subset of conductive pillars but not over the remaining conductive pillars comprises forming the photoresist mask on the conductive layer only over each of the first subset of conductive pillars.

5. The method of claim 2 wherein etching to remove the conductive layer removes a sufficient portion of the conductive layer from over each of the conductive pillars that are not part of the first subset to expose a conductive surface recessed within the top surface of the substrate.

6. The method of claim 5 wherein a portion of the conductive layer that was thinned by the etching comprises the conductive surface.

7. The method of claim 5 wherein the conductive surface is that of a corresponding one of the conductive pillars that are not part of the first subset.

8. The method of claim 1 wherein forming the protrusion bump pad over each of the first subset of the conductive pillars comprises:

forming a photoresist mask on the conductive layer over each conductive pillar not in the first subset but not over the conductive pillars in the first subset;

adding additional conductive material to the portions of the conductive layer not covered by the photoresist masks;

removing the photoresist masks; and

etching to remove a sufficient portion of the conductive layer from over each of the conductive pillars that are not part of the first subset to expose a conductive surface recessed within the top surface of the substrate.

9. The method of claim 8 wherein a portion of the conductive layer that was thinned by the etching comprises the conductive surface.

10. The method of claim 8 wherein the conductive surface is that of a corresponding one of the conductive pillars that are not part of the first subset.

11. The method of claim 1 further comprising coupling the substrate with a semiconductor die package by reflowing solder bumps contacting the protrusion bump pad over each of the first subset of conductive pillars.

12. The method of claim 1 further comprising contacting one of the protrusion bump pads with a testing probe.

13. A method, comprising:

forming on a carrier a substrate comprising first and second subsets of conductive pillars extending therethrough, wherein the first subset of conductive pillars which each comprise a protrusion bump pad protruding from a surface of the substrate, and wherein the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate;

separating the substrate from the carrier;

providing a die comprising at least one integrated circuit chip; and

coupling the die to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

14. The method of claim 13 wherein the substrate is formed on a first side of the carrier and further comprising:

forming on a second side of the carrier a second substrate comprising third and fourth subsets of conductive pillars extending therethrough, wherein the third subset of conductive pillars which each comprise a protrusion bump pad protruding from a surface of the substrate, and wherein the fourth subset of conductive pillars each partially form a trace recessed within the surface of the substrate;

separating the second substrate from the carrier; and

coupling the second substrate to a second die via a second plurality of conductive bumps each extending between one of the protrusion bump pads of the third plurality and the die.

15. The method of claim 13 wherein the die is coupled to the substrate after the substrate is separated from the carrier.

16. A method comprising:

forming on a first side of a carrier a plurality of build-up layers, the build-up layers including stacked conductors forming a plurality of conductive pillars extending from a bottom surface of the build-up layers to a top surface of the build-up layers, the conductive pillars being embedded within stacked dielectric layers, wherein respective top surfaces of the respective conductive pillars extend above a top surface of a topmost dielectric layer of the stacked dielectric layers;

removing the build-up layers from the carrier;

recessing a first subset of the conductive pillars to have respective top surfaces below the top surface of the topmost dielectric layer while leaving a second subset of the conductive pillars having respective top surfaces extending above the top surface of the topmost dielectric layer; and

mounting an integrated circuit die to the second subset of the conductive pillars.

17. The method of claim 16 further comprising:

forming on a second side of a carrier a second plurality of build-up layers, the second build-up layers including stacked conductors forming a second plurality of conductive pillars extending from a bottom surface of the second build-up layers to a top surface of the second build-up layers, the second conductive pillars being embedded within stacked second dielectric layers, wherein respective top surfaces of the respective second conductive pillars extend above a top surface of a second topmost dielectric layer of the stacked second dielectric layers;

removing the second build-up layers from the carrier;

recessing a third subset of the second conductive pillars to have respective top surfaces below the top surface of the second topmost dielectric layer while leaving a fourth subset of the second conductive pillars having respective top surfaces extending above the top surface of the second topmost dielectric layer; and

mounting an integrated circuit die to the fourth subset of the second conductive pillars.

18. The method of claim 16 further comprising depositing additional conductive material on the second subset of the conductive pillars.

19. The method of claim 16 wherein the step of recessing a first subset of the conductive pillars comprises etching back the first subset of the conductive pillars while the second subset of the conductive pillars are covered.

20. The method of claim 16 wherein the step of mounting an integrated circuit die to the second subset of the conductive pillars comprises bonding the integrated circuit die to the second subset of the conductive pillars with solder.