Transistor and tunable inductance
First Claim
Patent Images
1. A transistor, comprising:
- a stack of at least one semiconductor layer and a plurality of metal layers,at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300,wherein the at least one drain region and the at least one source region are formed in the at least one semiconductor layer, andwherein a plurality of interconnected drain contact regions and a plurality of interconnected source contact regions are formed in the plurality of metal layers,wherein the at least one drain region is connected to a drain contact pad via an array of vertically stacked drain contact regions, wherein a first drain contact region is formed in a first metal layer and wherein a second drain contact region is formed in a second metal layer, andwherein the at least one source region is connected to a source contact pad via an array of vertically stacked source metal regions, wherein a first source metal region is formed in the first metal layer and wherein a second source metal region is formed in the second metal layer.
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Abstract
According to a first aspect embodiments provide a transistor including at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300.
12 Citations
19 Claims
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1. A transistor, comprising:
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a stack of at least one semiconductor layer and a plurality of metal layers, at least one gate region between at least one drain region and at least one source region, wherein a ratio between a width of the gate region and a length of the gate region exceeds 300, wherein the at least one drain region and the at least one source region are formed in the at least one semiconductor layer, and wherein a plurality of interconnected drain contact regions and a plurality of interconnected source contact regions are formed in the plurality of metal layers, wherein the at least one drain region is connected to a drain contact pad via an array of vertically stacked drain contact regions, wherein a first drain contact region is formed in a first metal layer and wherein a second drain contact region is formed in a second metal layer, and wherein the at least one source region is connected to a source contact pad via an array of vertically stacked source metal regions, wherein a first source metal region is formed in the first metal layer and wherein a second source metal region is formed in the second metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A transistor, comprising:
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a stack of at least one semiconductor layer and a plurality of metal layers; at least one drain region and at least one source region formed in the at least one semiconductor layer; and a stack of interconnected drain metal regions formed in the plurality of metal layers, wherein the stack of interconnected drain metal regions is electrically connected to the at least one drain region; a stack of interconnected source metal regions formed in the plurality of metal layers, wherein the stack of interconnected source metal regions is electrically connected to the at least one source region; wherein a maximum distance between a drain metal region and a source metal region of a same metal layer is smaller than or equal to a maximum distance between the at least one drain region and the at least one source region to yield an off-mode capacitance of the transistor above a predefined threshold. - View Dependent Claims (14, 15, 16, 17)
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- 18. A tunable inductance comprising a plurality of multi-finger field effect transistors, each multi-finger field effect transistor comprising multiple fingers, wherein a ratio between a width of a finger and a length of the finger exceeds 300, and wherein an inductance of a multi-finger field effect transistor depends on a dimension of a metallization associated with its multiple fingers.
Specification