Fin deformation modulation

• US 9,276,062 B2
• Filed: 10/01/2014
• Issued: 03/01/2016
• Est. Priority Date: 02/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Chih-Tang, Huang, Tai-Chun, Lien, Hao-Ming
• Primary Examiner(s): Nhu, David
• Application Number:
  US14/504,149
• Publication Number:
  US 20150014790A1
• Time in Patent Office: 517 Days
• Field of Search: 257/396, 257/347, 257/701, 257/760, 257/192, 257/213, 257/249, 257/288, 257/350, 257/509, 257/200, 257/201, 257/E21.006, 257/E21.014, 257/E21.027, 257/E21.058, 257/E21.077, 257/E21.17, 257/E21.227, 257/E21.229, 257/E21.244, 257/E21.267, 257/E21.304, 257/E21.311, 257/E21.546
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

Claims

1. An integrated circuit (IC) structure comprising:

a semiconductor substrate;

a first semiconductor strip and a second semiconductor strip over the semiconductor substrate;

a first Shallow Trench Isolation (STI) region between and contacting the first semiconductor strip and the second semiconductor strip, wherein the first STI region comprises a first dielectric region; and

a second STI region over the semiconductor substrate, wherein the second STI region comprises;

a second dielectric region; and

a third dielectric region over a bottom portion of the second dielectric region, wherein the first dielectric region and the second dielectric region are formed of a same dielectric material, and wherein the first STI region is free from dielectric regions formed of a same material as the third dielectric region.

2. The integrated circuit structure of claim 1, wherein the second dielectric region and the third dielectric region have a distinguishable interface therebetween.

3. The integrated circuit structure of claim 1, wherein the first STI region has a first lateral dimension, and the second STI region has a second lateral dimension greater than the first lateral dimension.

4. The integrated circuit structure of claim 1, wherein top portions of the first and the second semiconductor strips form a portion of a Fin Field-Effect Transistor (FinFET).

5. The integrated circuit structure of claim 1, wherein the second dielectric region has a height smaller than about 50 percent of heights of the first semiconductor strip and the second semiconductor strip.

6. The integrated circuit structure of claim 1, wherein the second dielectric region and the third dielectric region are formed of different materials.

7. The integrated circuit structure of claim 1 further comprising:

a gate dielectric on sidewalls and top surfaces of the first semiconductor strip and the second semiconductor strip; and

a gate electrode over the gate dielectric, wherein the gate electrode comprises portions overlapping the first STI region and the second STI region.

8. The integrated circuit structure of claim 1, wherein the first STI region further comprises a first liner dielectric layer underlying the first dielectric region, and the second STI region further comprises a second liner dielectric layer underlying the second dielectric region.

9. The integrated circuit structure of claim 8, wherein the first liner dielectric layer and the second liner dielectric layer are formed of a same dielectric material.

10. An integrated circuit (IC) structure comprising:

a semiconductor substrate;

a semiconductor strip over the semiconductor substrate;

a first Shallow Trench Isolation (STI) region contacting a first sidewall of the semiconductor strip, wherein the first STI region comprises;

a first liner dielectric layer;

a first dielectric region over the first liner dielectric layer; and

a second dielectric region over the first dielectric region; and

a second STI region contacting a second sidewall of the semiconductor strip, with the first sidewall and the second sidewall being opposite sidewalls of the semiconductor strip, wherein the second STI region comprises;

a second liner dielectric layer; and

a third dielectric region over and contacting the second liner dielectric layer, with the third dielectric region being a topmost region of the second STI region.

11. The integrated circuit structure of claim 10, wherein the second dielectric region and the third dielectric region are formed of a same dielectric material.

12. The integrated circuit structure of claim 10, wherein the first liner dielectric layer and the second liner dielectric layer are formed of a same dielectric material.

13. The integrated circuit structure of claim 10, wherein a top surface of the first dielectric region is curved, and wherein an entirety of the top surface of the third dielectric region is planar.

14. The integrated circuit structure of claim 10, wherein the first dielectric region further comprises an additional top surface coplanar with a top surface of the second dielectric region.

15. The integrated circuit structure of claim 10, wherein the second STI region has a lateral dimension greater than a lateral dimension of the first STI region.

16. An integrated circuit (IC) structure comprising:

a semiconductor substrate;

a first Shallow Trench Isolation (STI) region over the semiconductor substrate and having a first lateral dimension, wherein all dielectric layers in the first STI region have a first total count; and

a second STI region over the semiconductor substrate and having a second lateral dimension greater than the first lateral dimension, wherein all dielectric layers in the second STI region have a second total count greater than the first total count.

17. The integrated circuit structure of claim 16, wherein the second STI region has one layer more that the first STI region.

18. The integrated circuit structure of claim 16 further comprising a semiconductor strip with opposite sidewalls contacting the first STI region and the second STI region, wherein a top portion of the semiconductor strip is higher than top surfaces of the first STI region and the second STI region.

19. The integrated circuit structure of claim 18 further comprising:

a gate dielectric on sidewalls and a top surface of the top portion of the semiconductor strip; and

a gate electrode over the gate dielectric, wherein the gate electrode comprises portions overlapping the first STI region and the second STI region.

20. The integrated circuit structure of claim 16, wherein all dielectric materials in the first STI region also exist in the second STI region.