Fabricating stacked nanowire, field-effect transistors

• US 9,276,064 B1
• Filed: 11/07/2014
• Issued: 03/01/2016
• Est. Priority Date: 11/07/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zang, Hui, Bouche, Guillaume, Wells, Gabriel Padron
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US14/535,433
• Time in Patent Office: 480 Days
• Field of Search: 438/230, 438/595, 438/396, 438/283
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

Claims

1. A method comprising:

forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along sidewalls thereof, and the cut mask spacer overlying the sidewall spacer;

defining a stack structure by cutting through the multiple layers using the cut mask spacer and the gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and

providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the at least one other layer of the multiple layers to selectively expose the end surfaces thereof.

2. The method of claim 1, further comprising anisotropically etching the alignment mask spacer and the at least one other layer of the multiple layers to expose, in part, the at least one other layer of the multiple layers.

3. The method of claim 2, wherein the anisotropically etching the alignment mask spacer further aligns the at least one other layer of the multiple layers to the alignment mask spacer on the gate structure.

4. The method of claim 1, wherein the selectively etching the at least one layer of the multiple layers partially undercuts the gate structure.

5. The method of claim 1, wherein the cut mask spacer has a greater thickness on the sidewall spacer of the gate structure than a thickness of the alignment mask spacer on the sidewall spacer of the gate structure.

6. The method of claim 1, further comprising removing the cut mask spacer from the gate structure prior to providing the alignment mask spacer.

7. The method of claim 6, wherein the cut mask spacer has a greater thickness on the sidewall spacer of the gate structure than a thickness of the alignment mask spacer on the sidewall spacer of the gate structure.

8. The method of claim 1, wherein after the cutting and the selectively etching, the at least one layer of the multiple layers partially undercuts the gate structure, and the at least one other layer of the multiple layers extends laterally out past the gate structure.

9. The method of claim 1, wherein the multiple layers comprise a first semiconductor material layer and a second semiconductor material layer, wherein the at least one layer of the multiple layers selectively etched comprises the second semiconductor material layer, and the at least one other layer of the multiple layers comprises the first semiconductor material layer.

10. The method of claim 9, wherein the first semiconductor material layer comprises silicon, and the second semiconductor material layer comprises germanium or silicon-germanium.

11. The method of claim 1, wherein the multiple layers comprise multiple, alternating first and second semiconductor material layers.

12. The method of claim 11, wherein the multiple second semiconductor material layers comprise the at least one layer of the multiple layers.

13. The method of claim 12, wherein the multiple second semiconductor material layers comprise germanium or silicon-germanium.

14. The method of claim 11, wherein the multiple first semiconductor layers comprise the at least one other layer of the multiple layers.

15. The method of claim 14, wherein the multiple first semiconductor materials layers comprise silicon.

16. The method of claim 11, wherein at least one second semiconductor material layer of the multiple second semiconductor material layers has a greater thickness than at least one first semiconductor material layer of the multiple first semiconductor material layers.

17. The method of claim 16, wherein providing the alignment mask spacer comprises conformally wrapping the alignment mask spacer around exposed portions of the multiple first semiconductor material layers of the multiple, alternating first and second semiconductor material layers.

18. The method of claim 1, wherein the cut mask spacer comprises an oxide spacer, and the alignment mask spacer comprises a nitride spacer.

19. The method of claim 1, wherein the sidewall spacer comprises one of a nitride spacer or a low-k dielectric constant spacer.

20. The method of claim 1, wherein the substrate structure comprises an insulating layer disposed over a substrate, the multiple layers and the gate structure being disposed above the insulating layer.