Contact metallurgy for self-aligned high electron mobility transistor

• US 9,276,077 B2
• Filed: 05/21/2013
• Issued: 03/01/2016
• Est. Priority Date: 05/21/2013
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Basu, Anirban
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): ASHBAHIAN, ERIC K
• Application Number:
  US13/898,580
• Publication Number:
  US 20140346566A1
• Time in Patent Office: 1,015 Days
• Field of Search: 257/194, 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence

Abstract

A metallization scheme employing a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and second refractory metal barrier layer are free of nitrogen, and thus, do not introduce additional nitrogen into the compound semiconductor layer, while allowing diffusion of the Group IIIA element to form locally doped regions underneath the source region and the drain region. Ohmic contacts may be formed at a temperature as low as about 500° C. This enables fabrication of FET whose source and drain are self-aligned to the gate.

Claims

1. A semiconductor structure comprising a high electron mobility transistor (HEMT), wherein said HEMT comprises:

a substrate including a stack of a substrate compound semiconductor layer and a top compound semiconductor layer;

a gate stack including, from bottom to top, a gate electrode and a gate electrode contact structure, wherein said gate electrode is of unitary construction and comprises a lower vertical portion contacting a horizontal surface of a portion of said top compound semiconductor layer, a horizontal portion located on said lower vertical portion and extending beyond sidewalls of said lower vertical portion, and a first vertical arm portion and a second vertical arm portion extending upward from either end of said horizontal portion, said horizontal portion and said first and said second vertical arm portions defining a cavity, and wherein said gate contact structure is located over top surfaces of said first and said second vertical arm portions and sidewalls and a bottom of said cavity;

a source region contacting a first portion of a top surface of said top compound semiconductor layer; and

a drain region contacting a second portion of said top surface of said top compound semiconductor layer, wherein said second portion is laterally spaced from said first portion by a width of said horizontal portion of said gate electrode, and wherein each of said gate electrode contact structure, said source region, and said drain region comprises a vertical stack, from bottom to top, of a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer;

a source-side diffusion region located beneath said source region and comprising a first portion of said top compound semiconductor layer; and

a drain-side diffusion region located beneath said drain region and comprising a second portion of said top compound semiconductor layer,

wherein each of said first portion and said second portion of said to compound semiconductor layer is doped with said Group IIIA element from said Group IIIA element layer, and

wherein said source-side diffusion region and said drain-side diffusion region are laterally spaced from each other by a fluorine-doped region located within said portion of said top compound semiconductor layer and underlying said horizontal surface.

2. The semiconductor structure of claim 1, wherein said first refractory metal barrier layer and said second refractory metal barrier layer are essentially free of nitrogen.

3. The semiconductor structure of claim 1, wherein said first refractory metal barrier layer consists essentially of at least one first elemental refractory metal, and said second refractory metal barrier layer consists essentially of at least one second elemental refractory metal.

4. The semiconductor structure of claim 1, wherein said first refractory metal barrier layer and said second refractory metal barrier layer consist essentially of elemental molybdenum.

5. The semiconductor structure of claim 1, wherein said Group IIIA element layer consists essentially of aluminum.

6. The semiconductor structure of claim 1, wherein said lower vertical portion of said gate electrode has a first width, and said horizontal portion of said gate electrode includes a pair of sidewalls laterally spaced by said width that is greater than said first width.

7. The semiconductor structure of claim 6, wherein a sidewall of said source region and a sidewall of said first vertical arm portion are vertically coincident with one of said pair of sidewalls, and a sidewall of said drain region and a sidewall of said second vertical arm portion are vertically coincident with another of said pair of sidewalls.

8. The semiconductor structure of claim 1, wherein said horizontal surface is coplanar with said top surface of said top compound semiconductor layer.

9. The semiconductor structure of claim 1, wherein said horizontal surface is recessed below a plane of said top surface of said top compound semiconductor layer.

10. The semiconductor structure of claim 1, wherein a gate-side first refractory metal barrier layer within said gate electrode contact structure includes two horizontal portions vertically offset from each other and another portion contacting said sidewalls of said cavity and adjoined to said two horizontal portions.

11. The semiconductor structure of claim 10, wherein a source-side first refractory metal barrier layer within said source region and a drain-side first refractory metal barrier layer within said drain region have a same thickness as said gate-side first refractory metal barrier layer.

12. The semiconductor structure of claim 1, wherein material compositions and layer thicknesses of each of said first refractory metal barrier layers, said Group IIIA element layers, said second refractory metal barrier layers, and said oxidation-resistant metallic layers within said three vertical stacks for said source region, said drain region, and said gate electrode contact structure are the same.

13. The semiconductor structure of claim 1, wherein said source-side diffusion region further comprises a first portion of said substrate compound semiconductor layer, and said drain-side diffusion region further comprises a second portion of said substrate compound semiconductor layer, wherein each of said first portion and said second portion of said substrate compound semiconductor layer is doped with said Group IIIA element from said Group IIIA element layer.

14. The semiconductor structure of claim 1, wherein said horizontal surface of said portion of said top compound semiconductor layer is a topmost surface of said top compound semiconductor layer.