Gate overvoltage protection for compound semiconductor transistors

• US 9,276,097 B2
• Filed: 03/30/2012
• Issued: 03/01/2016
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Vielemeyer, Martin, Hutzler, Michael, Curatola, Gilberto, Pozzovivo, Gianmauro
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US13/435,447
• Publication Number:
  US 20130256699A1
• Time in Patent Office: 1,432 Days
• Field of Search: 257/77, 257/328, 257/315, 438/172, 438/391
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.

Claims

1. A transistor device, comprising:

a compound semiconductor body;

a drain disposed in the compound semiconductor body;

a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;

a gate operable to control the channel region; and

a gate overvoltage protection device connected between the source and the gate and comprising p-type and n-type silicon-containing semiconductor material,

wherein the compound semiconductor body comprises a doped SiC substrate and a SiC epitaxial layer on the doped SiC substrate, the source is electrically connected to the doped SiC substrate through a conductive via disposed in a first trench extending through the SiC epitaxial layer to the doped SiC substrate, the gate overvoltage protection device is disposed in a second trench extending through the SiC epitaxial layer to the doped SiC substrate, the second trench is insulated from the SiC epitaxial layer, and the gate overvoltage protection device comprises alternating regions of p-type and n-type SiC.

2. A transistor device according to claim 1, wherein an n-type SiC region of the gate overvoltage protection device is electrically connected to the gate and a p-type SiC region of the gate overvoltage protection device contacts the doped SiC substrate.

3. A transistor device according to claim 1, wherein the alternating regions of p-type and n-type SiC end prior to the doped SiC substrate, and wherein the gate overvoltage protection device is connected at one end to the gate and to the doped SiC substrate at an opposing end through a conductive via disposed in the second trench between the alternating regions of p-type and n-type SiC and the doped SiC substrate.

4. A transistor device according to claim 1, further comprising a device isolation region adjacent the source, and wherein the gate overvoltage protection device is laterally spaced apart from the source by the device isolation region.

5. A transistor device according to claim 1, wherein the gate overvoltage protection device comprises a first n-type SiC region disposed in the second trench and connected to the gate, a second n-type SiC region disposed in the second trench below the first n-type SiC region and connected to the source, and a p-type SiC region disposed in the second trench between the first and second n-type SiC regions, the transistor device further comprising:

a drain terminal connected to the drain;

a gate terminal connected to the gate;

a source terminal connected to the doped SiC substrate;

an additional terminal; and

a resistor or additional gate overvoltage protection device disposed in a third trench laterally spaced apart from the first and second trenches and extending through the SiC epitaxial layer to the doped SiC substrate, the resistor or additional gate overvoltage protection device connected to the doped SiC substrate at one end and to the additional terminal at an opposing end.

6. A transistor device, comprising:

a GaN semiconductor body;

a drain disposed in the GaN semiconductor body;

a source disposed in the GaN semiconductor body and spaced apart from the drain by a channel region;

a gate operable to control the channel region; and

a gate overvoltage protection device disposed in a first trench formed in the GaN semiconductor body and connected between the source and the gate, the gate overvoltage protection device comprising alternating p-type and n-type silicon regions.

7. A transistor device according to claim 6, wherein the GaN semiconductor body comprises a doped substrate and one or more compound semiconductor materials on the doped substrate, the source is electrically connected to the doped substrate by a second trench extending through the one or more compound semiconductor materials to the doped substrate, and the gate overvoltage protection device is electrically insulated from the one or more compound semiconductor materials.

8. A transistor device according to claim 7, wherein the gate overvoltage protection device is connected at one end to the gate and to the doped substrate at an opposing end through a conductive via disposed in the first trench between the alternating p-type and n-type silicon regions and the doped substrate.

9. A transistor device according to claim 7, further comprising:

a drain terminal connected to the drain;

a gate terminal connected to the gate and one of the silicon regions of the gate overvoltage protection device;

a source terminal connected to the doped substrate;

an additional terminal; and

a resistor or additional gate overvoltage protection device disposed in a third trench laterally spaced apart from the first and second trenches and extending through the one or more compound semiconductor materials with the resistor or additional gate overvoltage protection device connected to the doped substrate at one end and to the additional terminal at an opposing end.

10. A transistor device according to claim 7, wherein the gate overvoltage protection device comprises:

a first series of alternating p-type and n-type silicon regions disposed in the first trench and which connect the source to the doped substrate; and

a second series of alternating p-type and n-type silicon regions disposed in the second trench below the source and which connect the gate to the doped substrate, the second series of alternating p-type and n-type silicon regions being electrically insulated from the one or more compound semiconductor materials.

11. A transistor device according to claim 10, further comprising a device isolation region adjacent the source, wherein the source contacts the channel region at one side and is spaced apart from the second series of alternating p-type and n-type silicon regions by the device isolation region at a second side different than the first side.

12. A transistor device according to claim 10, wherein the gate overvoltage protection device is disposed in an inactive region of the transistor device, the source and gate extend from an active region of the transistor device to the inactive region, the first series of alternating p-type and n-type silicon regions connects the source to the doped substrate in the inactive region, and the second series of alternating p-type and n-type silicon regions connects the gate to the doped substrate in the inactive region.

13. A transistor device according to claim 10, further comprising:

a drain terminal connected to the drain;

a gate terminal connected to the gate;

a source terminal connected to the doped substrate; and

an additional terminal connected to the doped substrate.

14. A transistor device according to claim 10, wherein the first series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction, and wherein the second series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction.

15. A method of manufacturing a transistor device, comprising:

forming a drain and a source in a GaN semiconductor body with the drain and the source spaced apart by a channel region;

forming a gate operable to control the channel region;

forming a first trench in the GaN semiconductor body; and

forming a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device comprising alternating p-type and n-type silicon regions disposed in the first trench.

16. A method according to claim 15, wherein the GaN semiconductor body comprises a doped substrate and one or more compound semiconductor materials on the doped substrate, the method further comprising:

forming a second trench extending through the one or more compound semiconductor materials to the doped substrate;

electrically connecting the source to the doped substrate through the second trench; and

electrically insulating the first trench from the one or more compound semiconductor materials.

17. A method according to claim 16, further comprising:

forming a conductive via in a lower part of the first trench and in contact with the doped substrate;

forming the gate overvoltage protection device in an upper part of the first trench above the conductive via so that the gate overvoltage protection device is connected to the doped substrate at one end through the conductive via; and

connecting the gate overvoltage protection device at an opposing end to the gate.

18. A method according to claim 16, further comprising:

connecting a drain terminal to the drain;

connecting a gate terminal to the gate and one of the silicon regions of the gate overvoltage protection device;

connecting a source terminal to the doped substrate;

forming a third trench laterally spaced apart from the first and second trenches and extending through the one or more compound semiconductor materials;

forming a resistor or additional gate overvoltage protection device in the third trench so that the resistor or additional gate overvoltage protection device is connected to the doped substrate at one end;

connecting an additional terminal to an opposing end of the resistor or additional gate overvoltage protection device.

19. A method according to claim 16, wherein forming the gate overvoltage protection device comprises:

forming a first series of alternating p-type and n-type silicon regions in the first trench which connect the source to the doped substrate;

forming a second series of alternating p-type and n-type silicon regions in the second trench below the source which connect the gate to the doped substrate; and

electrically insulating the second trench from the one or more compound semiconductor materials.

20. A method according to claim 19, further comprising forming a device isolation region adjacent the source with the source contacting the channel region at one side and spaced apart from the second series of alternating p-type and n-type silicon regions by the device isolation region at a second side different than the first side.

21. A method according to claim 19, wherein forming the gate overvoltage protection device comprises:

forming the first and second trenches in an inactive region of the transistor device;

extending the source from an active region of the transistor device to the inactive region and over the first trench so that the source is connected to the doped substrate in the inactive region through the first series of alternating p-type and n-type silicon regions; and

extending the gate from the active region to the inactive region and over the second trench so that the gate is connected to the doped substrate in the inactive region through the second series of alternating p-type and n-type silicon regions.

22. A method according to claim 19, wherein the first series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction, and wherein the second series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction.