Master-slave multi-phase charging

• US 9,276,430 B2
• Filed: 10/29/2013
• Issued: 03/01/2016
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sporck, Christian G, Garcea, Giovanni, Hawawini, Shadi
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/065,752
• Publication Number:
  US 20140347001A1
• Time in Patent Office: 854 Days
• US Class Current: 1/1
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02J 2207/20 Charging or discharging characterised by the power electronics converter
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/00712 the cycle being controlled or terminated in response to electric parameters
• CPC Class Codes: H02J 7/007194 of the battery
• CPC Class Codes: H02J 7/02 for charging batteries from ac mains by converters

Abstract

A multi-phase charging circuit comprises a device that can be configured for master mode operation or slave mode operation. In master mode operation, the device generates a control signal and a clock signal to control operation of a switching circuit for generating charging current. In slave mode operation, the device receives externally generated control and clock signals to control operation of its switching circuit.

Claims

1. A circuit for a battery charger, the circuit comprising:

a switching circuit having a control input, a clock input, and a switching output configured to connect to an inductive element;

a charging terminal configured to electrically connect the inductive element to a battery terminal to provide power to charge a battery connected to the battery terminal;

a control terminal;

a clock terminal;

a control selector configured to operate in a first configuration that provides an internally generated control signal to the control terminal and the control input of the switching circuit, and to operate in a second configuration that provides an externally generated control signal received on the control terminal to the control input of the switching circuit; and

a clock selector configured to operate in a first configuration that provides an internally generated clock signal to the clock terminal and the clock input of the switching circuit, and to operate in a second configuration that provides an externally generated clock signal received on the clock terminal to the clock input of the switching circuit.

2. The circuit of claim 1 further comprising a first FET and a second FET connected to the switching output of the switching circuit, the first FET being connected to the second FET, the first FET and the second FET being switched ON and OFF by the switching circuit in accordance with control signal received on the control input and a clock signal received on the clock input.

3. The circuit of claim 1 further comprising a delay element that can be selectively connected by the clock selector between the clock input and the clock terminal to provide an externally generated clock signal received on the clock terminal to the clock input.

4. The circuit of claim 3 wherein the delay element is configured to provide a selectable phase shift of the externally generated clock signal.

5. The circuit of claim 1 further comprising a clock signal generator to generate the internally generated clock signal;

and

a delay element,

wherein the clock selector, when operating in the first configuration, connects the clock signal generator to the clock terminal and the clock input of the switching circuit,

wherein the clock selector, when operating in the second configuration, connects the delay element between the clock input and the clock terminal to provide an externally generated clock signal received on the clock terminal to the clock input.

6. The circuit of claim 5 wherein the delay element is configured to produce a phase shift of the externally generated clock signal.

7. The circuit of claim 1 further comprising a control signal generator to generate the internally generated control signal,

wherein the control selector, when operating in the first configuration, connects the control signal generator to the control terminal and the control input of the switching circuit,

wherein the control selector, when operating in the second configuration, connects the control terminal to the control input to provide an externally generated control signal received on the control terminal to the control input.

8. The circuit of claim 1 further comprising a selector input configured to connect to an external selection indicator, wherein the control selector and the clock selector operate in the first or second configuration depending on the selection indicator.

9. The circuit of claim 8 wherein the delay element is configured to produce a phase shift of the externally generated clock signal depending on the selection indicator.

10. The circuit of claim 8 wherein the external selection indicator is a digital signal.

11. The circuit of claim 8 wherein the external selection indicator is an analog signal.

12. The circuit of claim 8 wherein the external selection indicator comprises one or more resistor elements.

13. A method in a circuit comprising:

selecting a clock signal from either an internal clock signal generated by a clock generator of the circuit or an external clock signal provided at a clock terminal of the circuit;

selecting a control signal from either an internal control signal generated by a control signal generator of the circuit or an external control signal provided at a control terminal of the circuit; and

controlling a switching circuit using the selected clock signal and the selected control signal to produce power at a power output terminal of the circuit.

14. The method of claim 13, further comprising sensing a selection signal and selecting the clock signal and the control signal in response to the selection signal.

15. The method of claim 14, wherein sensing the selection signal includes sensing an external signal provided at a selection terminal of the circuit.

16. The method of claim 13, wherein when the external clock signal is selected then phase-shifting the external clock signal and controlling the switching circuit using the phase-shifted clock signal.

17. The method of claim 13, wherein when the internal clock signal is selected then providing the internal clock signal on the clock terminal of the circuit.

18. The method of claim 13, wherein when the internal control signal is selected then providing the internal control signal on the control terminal of the circuit.

19. The method of claim 13, further comprising charging a battery using the power produced at the power output terminal of the circuit.

20. A circuit comprising:

means for selecting a clock signal from either an internal clock signal generated by a clock generator of the circuit or an external clock signal provided at a clock terminal of the circuit;

means for selecting a control signal from either an internal control signal generated by a control signal generator of the circuit or an external control signal provided at a control terminal of the circuit; and

means for producing power at a power output terminal of the circuit using the selected clock signal and the selected control signal.