Integrated circuit process and bias monitors and related methods

• US 9,276,561 B2
• Filed: 07/24/2015
• Issued: 03/01/2016
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Clark, Lawrence T., Kidd, David A., Chen, Chao-Wu
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US14/808,358
• Publication Number:
  US 20150333738A1
• Time in Patent Office: 221 Days
• Field of Search: 331/57, 331/44
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Claims

1. A method, comprising:

in a stage of a ring oscillator circuit,

mirroring a reference current flowing through a reference transistor with a current mirror circuit to generate a mirrored current,

the current mirror circuit comprising mirror transistors of a first conductivity type having channels lengths substantially larger than that of the reference transistor, and

controlling transitions in a stage output signal in response to a stage input signal with a switching circuit according to the mirrored current, wherein

the stage input signal is a stage output signal of another stage of the ring oscillator circuit,

generating a body bias in response to a difference between an oscillating signal generated by the ring oscillator circuit and a target data; and

applying the body bias to transistors of an integrated circuit that includes the ring oscillator circuit.

2. The method of claim 1, wherein:

the target data is determined based on a center of characteristic data of the ring oscillator circuit.