Generating a wafer inspection process using bit failures and virtual inspection

• US 9,277,186 B2
• Filed: 01/16/2013
• Issued: 03/01/2016
• Est. Priority Date: 01/18/2012
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Yong, Poh Boon, Simon, George, Du, Yuezhong
• Primary Examiner(s): Kostak, Victor
• Application Number:
  US13/743,074
• Publication Number:
  US 20130182101A1
• Time in Patent Office: 1,140 Days
• Field of Search: 348 86- 87, 348/92, 348125-128, 382144-147, 382/149, 382/150
• US Class Current: 1/1
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 7/18 Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast

Abstract

Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.

Claims

1. A computer-implemented method for generating a wafer inspection process, comprising:

scanning a wafer with an inspection system to detect defects on the wafer;

storing output of one or more detectors of the inspection system during the scanning regardless of whether the output corresponds to the defects detected on the wafer;

separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected;

applying one or more defect detection methods to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations, wherein said applying comprises iteratively applying the one or more defect detection methods to the stored output corresponding to the first portion of the physical locations, comparing the defects detected at the first portion of the physical locations to the bit failures, and changing one or more parameters of the one or more defect detection methods until the defects are detected at the first portion of the physical locations; and

generating a water inspection process based on the defects detected by the one or more defect detection methods at the first portion of the physical locations, wherein said storing, separating, applying, and generating are performed with a computer system.

2. The method of claim 1, wherein the wafer is not used for any step of the method other than the scanning step.

3. The method of claim 1, further comprising determining the physical locations on the water that correspond to the bit failures based on results of the testing.

4. The method of claim 1, wherein the inspection system comprises an optical or electron beam inspection system.

5. The method of claim 1, further comprising designating the defects detected by the one or more defect detection methods at the first portion of the physical locations as killer defects.

6. The method of claim 1, wherein said separating comprises comparing coordinates of the defects reported by the inspection system to coordinates of the physical locations.

7. The method of claim 1, wherein said separating comprises converting coordinates of the defects reported by the inspection system to a bitmap domain and comparing bitmap domain coordinates of the bit failures to bitmap domain coordinates of the defects detected by the inspection system.

8. The method of claim 1, further comprising storing information for the first portion of the physical locations as hot spots for the applying step.

9. The method of claim 1, wherein said changing the one or more parameters of the one or more defect detection methods comprises altering one of the one or more defect detection methods that is applied to the stored output depending on the defects detected by applying another of the one or more defect detection methods to the stored output.

10. The method of claim 1, wherein said scanning comprises scanning the wafer with the inspection system after different layers have been formed on the wafer to detect the defects on the different layers, wherein the physical locations comprise physical locations on at least two of the different layers, and wherein the wafer inspection process is generated for one or more of the different layers.

11. The method of claim 1, further comprising acquiring input from a user for the one or more defect detection methods.

12. The method of claim 1, wherein the one or more defect detection methods comprise the same defect detection algorithm with different values for the one or more parameters of the same defect detection algorithm.

13. The method of claim 1, wherein the one or more defect detection methods comprise different defect detection algorithms.

14. The method of claim 1, wherein a first of the one or more defect detection methods uses the output generated by a first set of the one or more detectors, and wherein a second of the one or more defect detection methods uses the output generated by a second set of the one or more detectors that is different than the first set.

15. The method of claim 1, wherein generating the wafer inspection process comprises selecting at least one of the one or more defect detection methods for the wafer inspection process and at least one of the one or more detectors that will be used to generate output during the wafer inspection process that will be input to the at least one of the one or more defect detection methods.

16. The method of claim 1, wherein said generating comprises generating the wafer inspection process based on the defects detected by the one or more defect detection methods at the first portion of the physical locations in combination with the defects detected on the wafer by the inspection system at the second portion of the physical locations.

17. The method of claim 1, wherein said applying further comprises applying the one or more defect detection methods to the stored output corresponding to the first and second portions of the physical locations to detect the defects at the first and second portions of the physical locations.

18. The method of claim 17, wherein said generating comprises generating the wafer inspection process based on the defects detected by the one or more defect detection methods at the first and second portions of the physical locations.

19. A non-transitory computer-readable medium, storing program instructions executable on a computer system for performing a computer-implemented method for generating a wafer inspection process, wherein the computer-implemented method comprises:

storing output of one or more detectors of an inspection system during scanning of a wafer performed to detect defects on the wafer regardless of whether the output corresponds to the defects detected on the wafer;

separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected;

applying one or more defect detection methods to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations, wherein said applying comprises iteratively applying the one or more defect detection methods to the stored output corresponding to the first portion of the physical locations, comparing the defects detected at the first portion of the physical locations to the bit failures, and changing one or more parameters of the one or more defect detection methods until the defects are detected at the first portion of the physical locations; and

generating a wafer inspection process based on the defects detected by the one or more defect detection methods at the first portion of the physical locations.

20. A system configured to generate a wafer inspection process, comprising:

an inspection subsystem configured to scan a wafer to detect defects on the wafer; and

a computer subsystem configured for;

storing output of one or more detectors of the inspection subsystem during the scanning regardless of whether the output corresponds to the defects detected on the wafer;

separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected;

applying one or more defect detection methods to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations, wherein said applying comprises iteratively applying the one or more defect detection methods to the stored output corresponding to the first portion of the physical locations, comparing the defects detected at the first portion of the physical locations to the bit failures, and changing one or more parameters of the one or more defect detection methods until the defects are detected at the first portion of the physical locations; and

generating a wafer inspection process based on the defects detected by the one or more defect detection methods at the first portion of the physical locations.

21. The system of claim 20, wherein the wafer is not used for any step performed by the computer subsystem.

22. The system of claim 20, wherein the computer subsystem is further configured for determining the physical locations on the wafer that correspond to the bit failures based on results of the testing.

23. The system of claim 20, wherein the inspection subsystem comprises an optical or electron beam inspection subsystem.

24. The system of claim 20, wherein the computer subsystem is further configured for designating the defects detected by the one or more defect detection methods at the first portion of the physical locations as killer defects.

25. The system of claim 20, wherein said separating comprises comparing coordinates of the defects reported by the inspection subsystem to coordinates of the physical locations.

26. The system of claim 20, wherein said separating comprises converting coordinates of the defects reported by the inspection subsystem to a bitmap domain and comparing bitmap domain coordinates of the bit failures to bitmap domain coordinates of the defects detected by the inspection subsystem.

27. The system of claim 20, wherein the computer subsystem is further configured for storing information for the first portion of the physical locations as hot spots for the applying step.

28. The system of claim 20, wherein said applying further comprises altering one of the one or more defect detection methods that is applied to the stored output depending on the defects detected by applying another of the one or more defect detection methods to the stored output.

29. The system of claim 20, wherein the inspection subsystem is further configured to scan the wafer after different layers have been formed on the wafer to detect the defects on the different layers, wherein the physical locations comprise physical locations on at least two of the different layers, and wherein the wafer inspection process is generated for one or more of the different layers.

30. The system of claim 20, wherein the computer subsystem is further configured for acquiring input from a user for the one or more defect detection methods.

31. The system of claim 20, wherein the one or more defect detection methods comprise the same defect detection algorithm with different values for the one or more parameters of the same defect detection algorithm.

32. The system of claim 20, wherein the one or more defect detection methods comprise different defect detection algorithms.

33. The system of claim 20, wherein a first of the one or more defect detection methods uses the output generated by a first set of the one or more detectors, and wherein a second of the one or more defect detection methods uses the output generated by a second set of the one or more detectors that is different than the first set.

34. The system of claim 20, wherein generating the wafer inspection process comprises selecting at least one of the one or more defect detection methods for the wafer inspection process and at least one of the one or more detectors that will be used to generate output during the wafer inspection process that will be input to the at least one of the one or more defect detection methods.

35. The system of claim 20, wherein said generating comprises generating the wafer inspection process based on the defects detected by the one or more defect detection methods at the first portion of the physical locations in combination with the defects detected on the wafer by the inspection system at the second portion of the physical locations.

36. The system of claim 20, wherein said applying further comprises applying the one or more defect detection methods to the stored output corresponding to the first and second portions of the physical locations to detect the defects at the first and second portions of the physical locations.

37. The system of claim 36, wherein said generating comprises generating the wafer inspection process based on the defects detected by the one or more defect detection methods at the first and second portions of the physical locations.