Atom probe tomography sample preparation for three-dimensional (3D) semiconductor devices

• US 9,279,849 B2
• Filed: 08/18/2015
• Issued: 03/08/2016
• Est. Priority Date: 12/09/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kane, Terence L., Walsh, John M.
• Primary Examiner(s): Berman, Jack
• Assistant Examiner(s): Smith, David E
• Application Number:
  US14/828,594
• Publication Number:
  US 20150355266A1
• Time in Patent Office: 203 Days
• Field of Search: 438/10, 438/14, 438/17, 850/18
• US Class Current: 1/1
• CPC Class Codes: G01N 1/32 Polishing; Etching
• CPC Class Codes: G01Q 30/20 Sample handling devices or methods
• CPC Class Codes: G01Q 60/40 Conductive probes
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/2644 Adaptations of individual semiconductor devices to facilitate the testing thereof
• CPC Class Codes: G01R 31/2898 Sample preparation, e.g. removing encapsulation, etching sample preparation in general G01N1/00
• CPC Class Codes: H01J 2237/31749 Focused ion beam
• CPC Class Codes: H01J 37/317 for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation H01J37/36 takes precedence
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure is provided. The method may include measuring a capacitance-voltage (C-V) characteristic for the 3D field effect transistor device and identifying, based on the measured capacitance-voltage (C-V) characteristic, a Fin structure corresponding to the 3D field effect transistor device. The identified Fin structure is detached from the 3D field effect transistor device using a nanomanipulator probe tip. The detached Fin is then welded to the nanomanipulator probe tip using an incident focused ion beam having a voltage of less than about 1000 eV. The incident focused ion beam having a voltage of less than about 1000 eV is applied to a tip of the Fin that is welded to the nanomanipulator probe tip.

Claims

1. A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure, the method comprising:

identifying, based on a measured capacitance-voltage (C-V) characteristic, a defect associated with a Fin structure corresponding to the 3D field effect transistor device;

detaching, using a nanomanipulator, the Fin structure from the 3D field effect transistor device based on the measured capacitance-voltage (C-V) characteristic identifying the defect associated with the 3D field effect transistor device; and

welding the detached Fin having the identified defect to the nanomanipulator probe tip using an incident focused ion beam.

2. The method of claim 1, further comprising:

applying the incident focused ion beam having a voltage of less than about 1000 eV to a tip of the Fin that is welded to the nanomanipulator probe tip, wherein the tip of the Fin is sharpened by the focused ion beam; and

applying an atomic probe tomography measurement on the Fin that is sharpened by the focused ion beam.

3. The method of claim 2, wherein the tip of the Fin is sharpened to a diameter in the range of about 20 nm-100 nm.

4. The method of claim 1, wherein the measuring of the capacitance-voltage (C-V) characteristic for the 3D field effect transistor device comprises:

exposing first and second contact regions associated with the 3D field effect transistor device;

coupling a high-frequency impedance probe having a frequency range of about 5 Mhz to about 110 Mhz to an impedance analyzer;

coupling the high-frequency impedance probe to a first and a second atomic force probe tip;

coupling, using an atomic force microscope, the first atomic force probe tip to the exposed first contact region;

coupling, using the atomic force microscope, the second atomic force probe tip to the exposed second contact region; and

measuring the C-V characteristic for the 3D field effect transistor device on the impedance analyzer, the impedance analyzer applying an operating frequency corresponding to the frequency range of about 5 Mhz to about 110 Mhz to the first and second contact regions of the 3D field effect transistor device using the high-frequency impedance probe.

5. The method of claim 4, further comprising:

an XYZ manipulation stage that holds the high-frequency impedance probe, the XYZ manipulation stage manipulating the XYZ position of the high-frequency impedance probe for optimizing the measured C-V characteristic for the 3D field effect transistor device by controlling both a first physical tension associated with a first electrical conductor coupled to a ground connection of the high-frequency impedance, and a second physical tension associated with a second electrical conductor coupled to a signal conductor of the high-frequency impedance probe.

6. The method of claim 4, wherein the exposing of the first and second contact regions comprises:

applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency;

generating, from the Argon ion source, a collimated ion beam incident on a surface corresponding to the first and second contact regions for planar removal of layers of the surface; and

exposing the first and second contact regions underlying the surface using an end-point detector based on the planar removal of the layers.

7. The method of claim 6, wherein the generated collimated ion beam is incident on the surface of the semiconductor structure at an angle of about 3-12 degrees.

8. The method of claim 6, wherein the radio frequency (RF) comprises a 1.4 MHz signal.

9. The method of claim 6, wherein the end-point detector comprises a secondary ion mass spectroscopy (SIMS) detector.

10. The method of claim 6, wherein the planar removal of layers comprises removing layers of silicon nitride using etch selective hexafluoroethane (C₂F₆) gas.

11. The method of claim 6, wherein the planar removal of layers comprises removing layers of silicon oxide using etch selective tetrafluoromethane (CF₄) gas.

12. The method of claim 6, wherein the planar removal of layers comprises removing layers of copper metallization.

13. The method of claim 6, wherein the exposed first and second contact regions comprises tungsten studs coupled to the 3D field effect transistor device.

14. The method of claim 1, wherein the C-V measurement is utilized to determine doping concentration in the Fin structure.

15. The method of claim 4, wherein the high-frequency impedance probe is coupled to a first and a second electrical conductor, the first electrical conductor coupled to the ground connection of the high-frequency impedance probe and the second electrical conductor coupled to the signal conductor of the high-frequency impedance probe.

16. The method of claim 15, wherein the first electrical conductor is coupled to the first atomic force probe tip and the second electrical conductor is coupled to the second atomic force probe tip.

17. A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure, the method comprising:

applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency;

generating, from the Argon ion source, a collimated ion beam incident on a crystalline surface of the semiconductor structure for planar removal of layers of the crystalline surface;

exposing first and second contact regions underlying the crystalline surface associated with the 3D field effect transistor device based on the planar removal of the layers;

coupling a high-frequency impedance probe to an impedance analyzer;

coupling the high-frequency impedance probe to a first and a second atomic force probe tip;

coupling the first atomic force probe tip to the exposed first contact region;

coupling the second atomic force probe tip to the exposed second contact region;

measuring the C-V characteristic for the 3D field effect transistor device on the impedance analyzer, the impedance analyzer applying an operating frequency to the first and second contact regions associated with the 3D field effect transistor device using the high-frequency impedance probe; and

detaching, based on the measured C-V characteristic, a Fin structure from the 3D field effect transistor device.

18. The method of claim 17, wherein the incident focused ion beam is generated by an inductively coupled Gallium ion source having a voltage in the range of about 500 eV-1000 eV.

19. A method for atom probe tomography (APT) sample preparation from a three-dimensional (3D) field effect transistor device formed within a semiconductor structure, the method comprising:

identifying, based on a capacitance-voltage (C-V) characteristic measurement, a defect associated with a Fin structure corresponding to the 3D field effect transistor device;

removing a hardmask layer from a top surface of the Fin structure using a collimated ion beam generated by applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency;

applying a metallic coating to the Fin structure having the identified defect;

detaching the coated Fin structure having the identified defect from the 3D field effect transistor device using a nanomanipulator probe tip;

welding the detached coated Fin having the identified defect to the nanomanipulator probe tip using an incident focused ion beam; and

applying the incident focused ion beam to a tip of the Fin that is welded to nanomanipulator probe tip.

20. The method of claim 19, wherein the metallic coating comprises a thickness of about 10 nm-30 nm.