Display driving circuit with photo detecting input

• US 9,280,236 B2
• Filed: 11/20/2013
• Issued: 03/08/2016
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: Egis Technology Inc.
• Original Assignee: Integrated Digital Technologies, Inc. (InterDigital, Inc.)
• Inventors: Hwang, Naejye, Liaw, Shen-Tai, Chang, Yang-Hui
• Primary Examiner(s): Bolotin, Dmitriy
• Application Number:
  US14/084,629
• Publication Number:
  US 20140139490A1
• Time in Patent Office: 839 Days
• Field of Search: 345173-178, 178/18.09
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133 Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36
• CPC Class Codes: G02F 1/13312 Circuits comprising photodetectors for purposes other than feedback
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G06F 3/0421 by interrupting or reflecting a light beam, e.g. optical touch-screen
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2360/142 the light being detected by light detection means within each pixel
• CPC Class Codes: G09G 5/00 Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators image data processing or generation, in general G06T

Abstract

A display driving circuit with photo detecting input includes pixel regions, pixel electrodes, gate lines, data lines, at least one photo detecting unit and at least one readout line. The gate lines cross the data lines. The data lines include a first data line and a second data line disposed adjacently to each other. There is no data line disposed between the first data line and the second data line. The photo detecting unit is electrically connected to one of the gate lines. The readout line is electrically connected to the photo detecting unit and disposed between the first data line and the second data line. A first spacing between first data line and the readout line is wider than or equal to a second spacing between the second data line and the readout line, and the first spacing is smaller than or equal to triple the second spacing.

Claims

1. A display driving circuit with photo detecting input, comprising:

a plurality of pixel regions, arranged in a matrix configuration;

a plurality of pixel electrodes, disposed in the pixel regions respectively;

a plurality of gate lines, extending along a first direction and disposed parallel to one another;

a plurality of data lines, extending along a second direction and disposed parallel to one another, wherein the gate lines cross the data lines, the data lines comprise a first data line and a second data line disposed adjacently to each other, and none of the data lines is disposed between the first data line and the second data line;

at least one photo detecting unit, disposed in at least one of the pixel regions, wherein the photo detecting unit is electrically connected to one of the gate lines; and

at least one readout line, electrically connected to the photo detecting unit, wherein the readout line is disposed between the first data line and the second data line, a first spacing between the first data line and the readout line is wider than a second spacing between the second data line and the readout line, and the first spacing is smaller than or equal to triple the second spacing.

2. The display driving circuit of claim 1, wherein the first spacing is smaller than or equal to double the second spacing.

3. The display driving circuit of claim 1, wherein the pixel regions are defined by the crossed gate lines and data lines, and the readout line at least partially overlaps the pixel electrodes along a vertical projective direction.

4. The display driving circuit of claim 1, further comprising a plurality of common lines extending along the first direction and disposed parallel to one another, wherein the photo detecting unit is electrically connected to one of the common lines.

5. The display driving circuit of claim 1, further comprising a plurality of common lines extending along the second direction and disposed parallel to one another, wherein the photo detecting unit is electrically connected to one of the common lines.

6. The display driving circuit of claim 1, further comprising a plurality of common electrodes disposed in the pixel regions respectively, wherein the photo detecting unit is electrically connected to at least one of the common electrodes.

7. The display driving circuit of claim 1, further comprising a plurality of display switching devices disposed in the pixel regions respectively, wherein each of the display switching devices is electrically connected to one of the gate lines, one of the data lines and one of the pixel electrodes.

8. The display driving circuit of claim 1, wherein the pixel electrodes comprising a first pixel electrode and a second pixel electrode disposed adjacently to each other along the first direction, and none of the pixel electrodes is disposed between the first pixel electrode and the second pixel electrode.

9. The display driving circuit of claim 8, wherein the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line.

10. The display driving circuit of claim 9, wherein the readout line is disposed between the first pixel electrode and the second pixel electrode.

11. The display driving circuit of claim 1, wherein the data lines further comprises at least one third data line disposed adjacently to the second data line along the first direction, wherein none of the data lines and none of the pixel electrodes are disposed between the second data line and the third data line.

12. The display driving circuit of claim 1, wherein the readout line is perpendicular to the gate lines.

13. The display driving circuit of claim 1, wherein the photo detecting unit comprises a photo sensing device.