Method of compressing data and device for performing the same
First Claim
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1. A data compression method comprising:
- receiving an input data stream including a previous data block and a current data block;
adjusting each delay of the current data block using a corresponding one of delay circuits and generating a first delayed data block and a second delayed data block;
executing a first comparison of only a part of the previous data block with only a part of a previous reference data block, and a second comparison of all of the first delayed data block with all of a current reference data block, wherein the first and second comparisons are executed in parallel; and
selectively, based on results of the first and second comparisons, outputting the second delayed data block or compressing an extended data block, wherein the extended data block includes the part of the previous data block and the second delayed data block,wherein a size of the current data block is greater than a size of the part of the previous data block, andwherein a size of the current reference data block is greater than a size of the part of the previous reference data block.
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Abstract
A data compression method includes receiving an input data stream including a previous data block and a current data block, and executing a first comparison of a part of the previous data block with part of a previous reference data block, and a second comparison of the current data block with a current reference data block, where the first and second comparisons are executed in parallel. The method further includes selectively, based on results of the first and second comparisons, outputting the current data block or compressing an extended data block, where the extended data block includes the part of the previous data block and the current data block.
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Citations
25 Claims
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1. A data compression method comprising:
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receiving an input data stream including a previous data block and a current data block; adjusting each delay of the current data block using a corresponding one of delay circuits and generating a first delayed data block and a second delayed data block; executing a first comparison of only a part of the previous data block with only a part of a previous reference data block, and a second comparison of all of the first delayed data block with all of a current reference data block, wherein the first and second comparisons are executed in parallel; and selectively, based on results of the first and second comparisons, outputting the second delayed data block or compressing an extended data block, wherein the extended data block includes the part of the previous data block and the second delayed data block, wherein a size of the current data block is greater than a size of the part of the previous data block, and wherein a size of the current reference data block is greater than a size of the part of the previous reference data block. - View Dependent Claims (2, 3, 4)
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5. A data compression method comprising:
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receiving an input data stream including a previous data block and a current data block; adjusting each delay of the current data block using a corresponding one of delay circuits and generating a first delayed data block and a second delayed data block; reading only a part of a previous reference data block from a memory, and in parallel reading a current reference data block from the memory; comparing only a part of the previous data block with only the part of the previous reference data block, and in parallel comparing the first delayed data block with the current reference data block; compressing an extended data block when the part of the previous data block matches the part of the previous reference data block, and the first delayed data block matches the current reference data block, wherein the extended data block includes the part of the previous data block and the second delayed data block, wherein a size of the current data block is greater than a size of the part of the previous data block, and wherein a size of the current reference data block is greater than a size of the part of the previous reference data block. - View Dependent Claims (6, 7, 8)
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9. A data compression circuit comprising:
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a buffer memory including a first memory region, a second memory region, and a third memory region; a buffer memory controller configured to output only a part of a previous reference data block stored in the first memory region and a current reference data block stored in the second memory region in response to an address output from a hash key generation circuit; an input data register configured to receive an input data stream, adjust each delay of a current data block included in the input data stream using a corresponding one of delay circuits and generate a first delayed data block and a second delayed data block; a comparison circuit configured to determine whether only a part of a previous data block matches only the part of the previous reference data block and whether the first delayed data block matches the current reference data block, and to generate control information according to a determination result; and a compressed-data generation circuit configured to selectively output, based on the control information, the second delayed data block or compressed data, wherein the compressed data is generated by compressing an extended data block which includes only the part of the previous data block and the second delayed data block, wherein a size of the current data block is greater than a size of the part of the previous data block, and wherein a size of the current reference data block is greater than a size of the part of the previous reference data block. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A data processing system comprising:
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a data storage device; a host configured to output a data stream including a previous data block and a current data block; and a memory controller comprising an input data register configured to receive the current data block, adjust each delay of the current data block using a corresponding one of delay circuits and generate a first delayed data block and a second delayed data block, wherein the memory controller is configured to determine a matching property of each data block or each extended data block in the data stream from the host, to compress the second delayed data block or the extended data block in the data stream according to a determination result, and to output compressed data to the data storage device, and wherein the memory controller determines the matching property of the previous data block, and then determines a matching property of the extended data block which includes a part of the previous data block and the second delayed data block, the memory controller further comprising a comparison circuit configured to determine in parallel whether the part of the previous data block matches a part of a previous reference data block and whether the first delayed data block matches a current reference data block, wherein a size of the current data block is greater than a size of the part of the previous data block, and wherein a size of the current reference data block is greater than a size of the part of the previous reference data block. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification