Compiler retargeting based on instruction semantic models

• US 9,280,326 B1
• Filed: 05/26/2005
• Issued: 03/08/2016
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Braun, Gunnar, Hoffmann, Andreas, Greive, Volker, Leupers, Rainer, Ceng, Jianjiang
• Primary Examiner(s): Zhen, Li B
• Assistant Examiner(s): Bodden, Evral
• Application Number:
  US11/140,353
• Time in Patent Office: 3,939 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 8/37 Compiler construction; Parser generation

Abstract

Generating a description of compiler code selector rules from an architecture description. A method comprises accessing a target architecture model written in an architecture description language (ADL) and extracting semantic information therefrom to generate a plurality of semantic statements. Rules that map from source code operations to semantic patterns are accessed. The semantic statements are searched for matches for the semantic patterns to generate mappings that serve as a description of compiler code selector rules.

Claims

1. A computer implemented method for generating a description of compiler code selector rules from an architecture description, the compiler code selector rules for use in a compiler that translates source code into machine instructions of a target processor, the method comprising:

accessing a target processor architecture model of the target processor, the target processor architecture model described in a processor architecture description language, the target processor architecture model comprising semantic information and syntax information for the machine instructions, and description of non-terminals of the target processor;

generating a plurality of semantic statements from semantic information included in the processor architecture model;

applying, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements;

generating a plurality of basic rules that map from source code operations to machine instructions comprising;

accessing rules that map from source code operations to semantic patterns,

searching said semantic statements for matches to said semantic patterns, and

mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that matches from semantic statements to semantic patterns; and

permuting said basic rules with non-terminals to generate a plurality of mappings that serve as said description of said compiler code selector rules.

2. The method of claim 1, further comprising extracting assembly code syntax from said target processor architecture model and associating said assembly code syntax with said semantic statements.

3. The method of claim 1, wherein said pre-defined semantic transformations comprise transformations that map from a single semantic statement to a plurality of semantic statements.

4. The method of claim 1, wherein said searching comprises mapping a single source code operation to a single machine instruction.

5. The method of claim 1, wherein said searching comprises mapping a single source code operation to more than one machine instruction.

6. The method of claim 1, further comprising creating a tree pattern for a rule not in said accessed rules by analyzing a complex semantic statement of said plurality of semantic statements.

7. A non-transitory computer readable medium configured to store instructions for generating a description of compiler selector rules from an architecture description, the compiler selector rules for use in a compiler that translates source code into machine instructions of a target processor, the instructions when executed by a processor cause the processor to:

access a target processor architecture model of the target processor, the target processor architecture model written in a processor architecture description language, the target processor architecture model comprising semantic information and syntax information for the machine instructions, and description of non-terminals of the target processor;

generate a plurality of semantic statements from semantic information included in the processor architecture model;

apply, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements;

generate a plurality of basic rules that map from source code operations to machine instructions comprising;

accessing rules that map from source code operations to semantic patterns,

searching said semantic statements for matches, and

mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that matches from semantic statements to semantic patterns; and

permute said basic rules with said non-terminals to generate a plurality of mappings that serve as said description of said compiler code selector rules.

8. The computer readable medium of claim 7, further comprising a library of pre-defined semantic transformations that are operable to transform said extracted semantic information.

9. The computer readable medium of claim 7, wherein said instructions further cause the processor to extract assembly code syntax from said target processor architecture model and associating assembly code syntax with each of said plurality of semantic statements.

10. The computer readable medium of claim 7, wherein the instructions for searching said semantic statements for matches to said semantic patters cause the processor to map a single source code operation to a single machine instruction.

11. The computer readable medium of claim 7, wherein the instructions for searching said semantic statements for matches to said semantic patters cause the processor to map a single source code operation to more than one machine instruction.

12. The computer readable medium of claim 7, wherein said target processor architecture model comprises a hierarchical format.

13. A computer implemented method for generating compiler code selector rules from an architecture description, the compiler code selector rules for use in a compiler that translates source code into machine instructions of a target processor, the method comprising:

generating a plurality of semantic statements from semantic information included in a target processor architecture model of a target processor, the target processor architecture model described in a processor architecture description language, said semantic information describing an instruction set, wherein said target processor architecture model comprises semantic information and syntax information for the machine instructions, and description of non-terminals of the target processor;

associating assembly syntax with semantic information;

applying, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements;

accessing basic rules having tree patterns that map from source code operations to semantic patterns;

permuting said basic rules based on said non-terminals to form set of permuted mapping rules; and

matching semantic patterns of said permuted mapping rules to said semantic statements to form a description of said complier code selector rules comprising mappings from source code operations to associated assembly syntax; and

mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that matches from semantic statements to semantic patterns.

14. The method of claim 13, wherein said matching semantic patterns comprises mapping a single source code operation to a single machine instruction.

15. The method of claim 13, wherein said matching semantic patterns of said permuted mapping rules to said extracted semantic information comprises mapping a single source code operation to more than one machine instruction.

16. The method of claim 13, wherein said non-terminals represent locations in which to store intermediate results.

17. The method of claim 13, wherein said extracted semantic information comprise micro-operators.

18. The method of claim 13, further comprising inputting a compiler description comprising said description of compiler code selector rules to an automatic compiler generation tool to automatically generate a compiler adapted to said target processor architecture.

19. The method of claim 13, further comprising creating a tree pattern for a rule not in said basic rules by analyzing a complex semantic statement of said extracted semantic information.