Data processing device

• US 9,280,341 B2
• Filed: 12/31/2013
• Issued: 03/08/2016
• Est. Priority Date: 09/06/2002
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ohtani, Sugako, Kondo, Hiroyuki
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/144,822
• Publication Number:
  US 20140115303A1
• Time in Patent Office: 798 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.

Claims

1. A data processing device comprising:

an instruction decoder for decoding an instruction code in an arithmetic instruction;

a controller for detecting an effective data width of operation data to be processed for the arithmetic instruction, for detecting data type information specifying whether or not the operation data include a sign, and, based on the decode result from the instruction decoder, for determining an instruction execution cycle number which is the number of cycles of execution of the arithmetic instruction corresponding to the detected effective data width and the data type information; and

an arithmetic operation unit for executing the arithmetic instruction with the number of cycles for the instruction execution determined by the controller.

2. The data processing device as claimed in claim 1, wherein the instruction code of the arithmetic instruction includes size upper-limit information to specify the upper limit value for a range of searching for use in the detection of the effective data width of the operation data, and

the controller searches the operation data in the range based on the upper limit value specified by the size upper limit information in order to detect the effective data width, and determines the number of cycles for the instruction execution corresponding to the effective data width.

3. The data processing device as claimed in claim 1, further comprises a memory unit for storing instruction code information to control the instruction execution cycle number of the arithmetic instruction, and

wherein the controller determines the instruction execution cycle number corresponding to the effective data width of the operation data to be processed in the arithmetic instruction based on the instruction code information read from the memory unit.

4. The data processing device as claimed in claim 3, wherein the memory unit stores data type information to specify the presence of a sign in the operation data as the instruction code information, and

wherein the controller detects the effective data width according to the presence of the sign in the operation data specified in the data type information, and determines the instruction execution cycle number corresponding to the effective data width detected.

5. The data processing device as claimed in claim 3, wherein the memory unit stores size upper limit information as the instruction code information to specify a upper limit value of a searching range when the effective data width of the operation data is detected, and

wherein the controller detects the effective data width by searching the operation data within the range based on the upper limit value specified in the size upper limit information, and determines the instruction execution cycle number corresponding to the effective data width obtained.

6. The data processing device as claimed in claim 3, wherein the memory unit stores process setting information to specify whether or not the controller detects the effective data width of the operation data, and

wherein the controller sets a data width based on the instruction code information as the effective data width when the process setting information read from the memory unit indicates not to execute the detection for the effective data width, and determines the instruction execution cycle number corresponding to the effective data width obtained.

7. The data processing device as claimed in claim 6, wherein the process setting information has information to define whether the instruction code information is valid or invalid, and

wherein the control unit sets a predetermined data width as the effective data width of the operation data when the process setting information indicate the information not to detect the effective data width and the instruction code information is invalid, and determines the instruction execution cycle number corresponding to the effective data width obtained.