Generating a circuit description for a multi-die field-programmable gate array

• US 9,280,629 B2
• Filed: 11/04/2014
• Issued: 03/08/2016
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Emirian, Frederic
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US14/532,010
• Publication Number:
  US 20150135147A1
• Time in Patent Office: 490 Days
• Field of Search: 716/105
• US Class Current: 1/1
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation.

Claims

1. A method for generating a circuit description for a multi-die field-programmable gate array (FPGA) comprising a first FPGA die and at least one further FPGA die, the method being performed in an FPGA design tool and comprising:

evaluating, automatically, a first partition and a second partition of a partitioned circuit description, the first partition being associated with the first FPGA die and the second partition being associated with the at least one further FPGA die; and

inserting at least one multiplexing element into the first partition and a corresponding de-multiplexing element into the second partition based on the automated evaluation.

2. The method of claim 1, wherein the at least one multiplexing element and the corresponding de-multiplexing element are designed for performing a time-multiplexed transmission of a plurality of logical signals over a single physical inter-die connection from the first FPGA die to the at least one further FPGA die.

3. The method of claim 2, wherein the inserting step further comprises inserting clock synchronizing elements designed for a clock synchronization between the at least one multiplexing element and the corresponding de-multiplexing element.

4. The method of claim 1, wherein the evaluating step comprises identifying a set of logical signals in the circuit description being emitted from the first partition and being received in the second partition, and wherein the at least one multiplexing element and the corresponding de-multiplexing element are inserted for a subset of the set of identified logical signals.

5. The method of claim 1, wherein the first FPGA die and the at least one further FPGA die are located adjacent within the multi-die FPGA.

6. The method of claim 1, wherein:

the multi-die FPGA comprises the first FPGA die, a second FPGA die, to which the second partition is associated, and at least a third FPGA die, to which a third partition of the partitioned circuit description is associated;

the at least third FPGA die is located between the first FPGA die and the second FPGA die; and

based on the evaluation, the at least one multiplexing element is inserted into the first partition, the corresponding de-multiplexing element is inserted into the second partition, and an intermediate register being coupled between the at least one multiplexing element and the corresponding de-multiplexing element is inserted into the third partition.

7. The method of claim 6, wherein selecting elements associated with the at least one multiplexing element and the corresponding de-multiplexing element are inserted additionally, wherein the selecting element of the de-multiplexing element is shifted with respect to the selecting element of the at least one multiplexing element based on a delay of the intermediate register.

8. The method of claim 3, wherein the circuit description is a netlist description.

9. The method of claim 2, wherein the partitioned circuit description is generated by partitioning an input circuit description prior to the evaluating step.

10. The method of claim 1, wherein the method is performed for multiple combinations of FPGA dies of the multi-die FPGA.

11. The method of claim 2, further comprising compiling the partitioned circuit description after the inserting step in order to receive a program code for the multi-die FPGA.

12. A computer program product comprising a non-transitory computer readable storage medium storing program code, said code when executed by a processor causes the processor to:

evaluate a first partition and a second partition of a partitioned circuit description, the first partition being associated with the first FPGA die and the second partition being associated with the at least one further FPGA die; and

insert at least one multiplexing element into the first partition and a corresponding de-multiplexing element into the second partition based on the automated evaluation.

13. The computer program product of claim 12, wherein the at least one multiplexing element and the corresponding de-multiplexing element are designed for performing a time-multiplexed transmission of a plurality of logical signals over a single physical inter-die connection from the first FPGA die to the at least one further FPGA die.

14. The computer program product of claim 13, wherein the instructions that cause the processor to insert step further comprises instructions that cause the processor to insert clock synchronizing elements designed for a clock synchronization between the at least one multiplexing element and the corresponding de-multiplexing element.

15. The computer program product of claim 12, wherein the instructions that cause the processor to evaluate further comprises instructions that cause the processor to identify a set of logical signals in the circuit description being emitted from the first partition and being received in the second partition, and wherein the at least one multiplexing element and the corresponding de-multiplexing element are inserted for a subset of the set of identified logical signals.

16. The computer program product of claim 12, wherein the first FPGA die and the at least one further FPGA die are located adjacent within the multi-die FPGA.

17. The computer program product of claim 12, wherein:

the multi-die FPGA comprises the first FPGA die, a second FPGA die, to which the second partition is associated, and at least a third FPGA die, to which a third partition of the partitioned circuit description is associated, the at least third FPGA die is located between the first FPGA die and the second FPGA die.

18. The computer program product of claim 17, further comprising selecting elements associated with the at least one multiplexing element and the corresponding de-multiplexing element are inserted additionally, wherein the selecting element of the de-multiplexing element is shifted with respect to the selecting element of the at least one multiplexing element based on a delay of the intermediate register.

19. The computer program product of claim 13, wherein the partitioned circuit description is generated by partitioning an input circuit description prior to the instructions that cause the processor to evaluate.

20. The computer program product of claim 12, further comprising compiling the partitioned circuit description after the inserting step in order to receive a program code for the multi-die FPGA.