Systems and methods for reducing standby power in floating body memory devices

• US 9,281,022 B2
• Filed: 07/10/2014
• Issued: 03/08/2016
• Est. Priority Date: 07/10/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Widjaja, Yuniarto
• Primary Examiner(s): Le, Vu
• Application Number:
  US14/328,633
• Publication Number:
  US 20150016207A1
• Time in Patent Office: 607 Days
• Field of Search: 365/185.05, 365/185.18, 365/185.08
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

Claims

1. A method of tracking the state of a floating body memory cell for turning on and off a vertical bipolar holding mechanism to ensure that a state of the floating body memory cell is maintained, said method comprising:

providing a reference cell that measures a potential level of the floating body of the floating body memory cell;

providing a high level floating body potential detector and a low level floating body potential detector;

inputting the potential level of the floating body to the high and low level floating body potential detectors;

receiving output signals from the high and low level floating body potential detector by a controller; and

controlling a voltage regulator to control a voltage level input to a source line, bit line or DNWell line of the floating body memory cell to turn off or turn on the vertical bipolar holding mechanism based upon input signals received from the high level floating body potential detector and the low level floating body potential detector.

2. The method of claim 1,

wherein when the low level floating body potential detector inputs a signal to the controller indicating that a predetermined low potential has been measured, said controller controls said voltage regulator to increase the voltage level input to the source line or bit line to turn on the vertical bipolar holding mechanism;

and

wherein when the high level floating body potential detector inputs a signal to the controller indicating that a predetermined high potential has been measured, said controller controls said voltage regulator to turn off the voltage level input to the source line or bit line to turn off the vertical bipolar holding mechanism.

3. The method of claim 1,

wherein when the low level floating body potential detector inputs a signal to the controller indicating that a predetermined low potential has been measured, said controller controls said voltage regulator to turn off the voltage level input to the DNWell line to turn on the vertical bipolar holding mechanism;

and

wherein when the high level floating body potential detector inputs a signal to the controller indicating that a predetermined high potential has been measured, said controller controls said voltage regulator to increase the voltage level input to the DNWell line to turn off the vertical bipolar holding mechanism.

4. The method of claim 3, further comprising:

providing a plurality of said DNWell lines, source lines or bit lines;

connecting said plurality of DNWell lines, source lines or bit lines with a plurality of equalization transistors;

inputting a signal to said plurality of equalization transistors to turn on said equalization transistors to equalize charge among said plurality of said DNWell lines, source lines or bit lines, prior to said controlling said voltage regulator; and

turning off said equalization transistors prior to said controlling said voltage regulator.