Memory timing circuit
First Claim
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1. A memory circuit, comprising:
- a memory cell configured to provide a charge, voltage, or current to an associated bit-line;
a sense amplifier configured to sense the charge, voltage, or current on the bit-line;
a word-line circuit configured to control a word-line of the memory cell;
a bit-line circuit having at least one of (i) a bit-line voltage control circuit and (ii) a mux circuit; and
a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control at least one of;
(i) the word-line circuit, and (ii) bit-line circuit, wherein the tracking circuit comprises;
a reference sense amplifier;
a reference bit-line; and
a reference element configured to provide a reference charge, voltage, or current to the reference bit-line, wherein the reference sense amplifier and the reference bit-line have a configuration substantially similar to the bit-line and sense amplifier.
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Abstract
A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.
13 Citations
16 Claims
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1. A memory circuit, comprising:
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a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; a bit-line circuit having at least one of (i) a bit-line voltage control circuit and (ii) a mux circuit; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control at least one of;
(i) the word-line circuit, and (ii) bit-line circuit, wherein the tracking circuit comprises;a reference sense amplifier; a reference bit-line; and a reference element configured to provide a reference charge, voltage, or current to the reference bit-line, wherein the reference sense amplifier and the reference bit-line have a configuration substantially similar to the bit-line and sense amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of controlling a memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line, a bit-line circuit, a sense amplifier configured to sense the charge, voltage, or current on the bit-line, a word-line circuit configured to control a word-line of the memory cell, and a tracking circuit, the method comprising:
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tracking one or more conditions of the bit-line of the memory circuit by the tracking circuit; and providing a timing control signal to at least one of (i) the word-line circuit and (ii) bit-line circuit of the memory circuit to adaptively control the word-line circuit based on the tracking providing a reference charge, voltage, or current to a reference bit-line, wherein a reference sense amplifier and a reference bit-line have a configuration substantially similar to the bit-line and sense amplifier. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification