Semiconductor test system and operation method of the same

• US 9,281,067 B1
• Filed: 08/11/2014
• Issued: 03/08/2016
• Est. Priority Date: 08/11/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Hong Gab, Choi, Mansik, Ye, Byoungwoo
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/456,600
• Time in Patent Office: 575 Days
• Field of Search: 365/222, 365/185, 365/185.1, 714/6.21, 714/30
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals

Abstract

A semiconductor test system includes a nonvolatile memory and a test device. The nonvolatile memory is configured to include an information region. The test device is configured to include a pin memory and a pin memory controller. The pin memory controller is configured to separate information data into a plurality of information data groups, sequentially transmit the separated plurality of information data groups to the pin memory, sequentially transmit the transmitted plurality of information data group in the pin memory to the nonvolatile memory, and program the transmitted plurality of information data group in the nonvolatile memory into the information region.

Claims

1. A semiconductor test system comprising:

a nonvolatile memory configured to include an information region; and

a test device configured to include a pin memory and a pin memory controller,

wherein the pin memory controller is configured to divide information data into a plurality of information data groups if a size of the information data is bigger than a size of the pin memory, sequentially transmit the divided plurality of information data groups to the pin memory, sequentially transmit the plurality of information data groups of the pin memory to the nonvolatile memory, and program the plurality of information data groups of the nonvolatile memory into the information region.

2. The semiconductor test system of claim 1, wherein the information region is configured to store single bit data.

3. The semiconductor test system of claim 1, wherein the nonvolatile memory includes a 3-dimensional memory cell array.

4. The semiconductor test system of claim 1, wherein the nonvolatile memory is configured to simultaneously program the plurality of the information data groups.

5. The semiconductor test system of claim 4, wherein

the plurality of information data groups include first and second information data groups,

the pin memory controller is configured to transmit a program set up command to the nonvolatile memory, and transmit the first information data group to the pin memory, and

the pin memory controller is configured to transmit a data input command to the nonvolatile memory, and transmit the second information data group to the pin memory.

6. The semiconductor test system of claim 5, wherein

the pin memory controller is configured to transmit a program confirm command to the nonvolatile memory,

the nonvolatile memory is configured to program the first and the second information data groups according to the program confirm command.

7. A method of operating a semiconductor test system including:

a nonvolatile memory including an information region and a test device including a pin memory and a pin memory controller, the method comprising,

generating a plurality of information data sets based on information data if a size of the information data is bigger than a size of the pin memory;

sequentially transmitting each of the plurality of information data sets to the pin memory;

transmitting each of the information data sets from the pin memory to the nonvolatile memory; and

if all of the information data sets are transmitted to the nonvolatile memory, programming the plurality of information data sets into the information region.

8. The method of claim 7, wherein the programming programs the plurality of information data sets with single bit data.

9. The method of claim 7, wherein the nonvolatile memory includes 3-dimensional memory cell array.

10. The method of claim 7, wherein the programming is to program simultaneously the plurality of information data sets into the information region.

11. The method of claim 10, wherein the plurality of information data sets includes a first and a second information data set, the transmitting each of information data sets from the pin memory to the nonvolatile memory further comprising:

transmitting the first information data set to the nonvolatile memory after transmitting a program set up command to the nonvolatile memory; and

transmitting the second information data set to the nonvolatile memory after transmitting a data input command to the nonvolatile memory.

12. The method of claim 11, wherein the programming includes:

transmitting a program confirm command to the nonvolatile memory; and

simultaneously programming the first and the second information data sets into the information region.