Method of programming a nonvolatile memory device

• US 9,281,069 B2
• Filed: 05/09/2014
• Issued: 03/08/2016
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Joon-Suc, Kwak, Dong-Hun
• Primary Examiner(s): King, Douglas
• Application Number:
  US14/274,041
• Publication Number:
  US 20140247657A1
• Time in Patent Office: 669 Days
• Field of Search: 365/185.02, 365/185.18, 365/185.22, 365/185.24, 365/185.03
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

In method of programming a nonvolatile memory device including a plurality of multi-level cells that store multi-bit data according to example embodiments, a least significant bit (LSB) program operation is performed to program LSBs of the multi-bit data in the plurality of multi-level cells. A most significant bit (MSB) program operation is performed to program MSBs of the multi-bit data in the plurality of multi-level cells. To perform the MSB program, an MSB pre-program operation is performed on first multi-level cells, from among the plurality of multi-level cells, that are to be programmed to a highest target program state among a plurality of target program states, and an MSB main program operation is performed to program the plurality of multi-level cells to the plurality of target program states corresponding to the multi-bit data.

Claims

1. A method of programming a nonvolatile memory device including a plurality of multi-level cells coupled to a wordline, the method comprising:

performing a least significant bit (LSB) program operation that programs LSBs of 2-bit data in the plurality of multi-level cells; and

performing a most significant bit (MSB) program operation that programs MSBs of the 2-bit data in the plurality of multi-level cells, the MSB program operation including,

an MSB pre-program operation that pre-programs first multi-level cells from among the plurality of multi-level cells to an intermediate program state, the first multi-level cells being ones of the plurality of multi-level cells that are to be programmed to a highest target program state among a plurality of target program states, and

an MSB main program operation, separate from the MSB pre-program operation, that programs the plurality of multi-level cells to the plurality of target program states corresponding to the 2-bit data by applying at least one program pulse to the plurality of multi-level cells, the MSB main program operation including a verify operation to verify that the plurality of multi-level cells are programmed to the plurality of target program states, and

the MSB pre-program operation comprising,

applying a program voltage to first bitlines coupled to the first multi-level cells,

applying an inhibit voltage to second bitlines coupled to second multi-level cells other than the first multi-level cells from among the plurality of multi-level cells, the second multi-level cells including ones of the plurality of multi-level cells that are to be programmed to one of the plurality of target program states adjacent to the highest target program state, and the inhibit voltage being higher than the program voltage, and

applying a one-shot pulse to the wordline to pre-program the first multi-level cells to the intermediate program state corresponding to the highest target program state,

wherein a verify operation for the intermediate program state is not performed.

2. The method of claim 1, wherein the first multi-level cells are programmed by the MSB main program operation from the intermediate program state to the highest target program state having a width narrower than a width of the intermediate program state.

3. The method of claim 1, wherein the one-shot pulse has a voltage level sufficient to substantially increase a threshold voltage of at least one of the first multi-level cells.

4. The method of claim 1, wherein the program voltage applied to the first bitlines during the MSB pre-program operation is a ground voltage.

5. The method of claim 1, wherein the program voltage applied to the first bitlines during the MSB pre-program operation is a voltage higher than a ground voltage.

6. A nonvolatile memory device comprising:

a memory cell array including a plurality of multi-level cells coupled to a wordline;

a voltage generator configured to generate a first incremental step pulse, a one-shot pulse, and a second incremental step pulse; and

a control circuit configured

to perform a least significant bit (LSB) program operation that programs LSBs of 2-bit data in the plurality of multi-level cells by using the first incremental step pulse, and

to perform a most significant bit (MSB) program operation that programs MSBs of the 2-bit data in the plurality of multi-level cells, the MSB program operation including,

an MSB pre-program operation that pre-programs first multi-level cells from among the plurality of multi-level cells to an intermediate program state by using the one-shot pulse, the first multi-level cells being ones of the plurality of multi-level cells that are to be programmed to a highest target program state among a plurality of target program states, and

an MSB main program operation, separate from the MSB pre-program operation, that programs the plurality of multi-level cells to the plurality of target program states corresponding to the 2-bit data by using the second incremental step pulse, the MSB main program operation including a verify operation to verify that the plurality of multi-level cells are programmed to the plurality of target program states, and

the MSB pre-program operation comprising,

applying a program voltage to first bitlines coupled to the first multi-level cells,

applying an inhibit voltage to second bitlines coupled to second multi-level cells other than the first multi-level cells from among the plurality of multi-level cells, the second multi-level cells including ones of the plurality of multi-level cells that are to be programmed to one of the plurality of target program states adjacent to the highest target program state, and the inhibit voltage being higher than the program voltage, and

applying the one-shot pulse to the wordline to pre-program the first multi-level cells to the intermediate program state corresponding to the highest target program state,

wherein a verify operation for the intermediate program state is not performed.

7. The nonvolatile memory device of claim 6, wherein the first multi-level cells are programmed by the MSB main program operation from the intermediate program state to the highest target program state having a width narrower than a width of the intermediate program state.

8. The nonvolatile memory device of claim 6, wherein the voltage generator generates the one-shot pulse having a voltage level sufficient to substantially increase a threshold voltage of at least one of the first multi-level cells.

9. The nonvolatile memory device of claim 6, wherein the program voltage applied to the first bitlines during the MSB pre-program operation is a ground voltage.

10. The nonvolatile memory device of claim 6, wherein the program voltage applied to the first bitlines during the MSB pre-program operation is a voltage higher than a ground voltage.