Method of manufacturing semiconductor memory device

• US 9,281,217 B1
• Filed: 05/28/2015
• Issued: 03/08/2016
• Est. Priority Date: 01/05/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Jung, Sung Wook, Lee, Dong Hun, Baek, Ji Hui, Lee, Tae Hwa, Heo, Hye Eun
• Primary Examiner(s): Tran, Long K
• Application Number:
  US14/724,517
• Time in Patent Office: 285 Days
• Field of Search: 438/702, 438/633, 438/638
• US Class Current: 1/1
• CPC Class Codes: H01L 21/47573 Etching the layer
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A method of manufacturing a semiconductor memory device includes forming a first attached layer on a substrate, forming a stack layer on the first attached layer, separating the stack layer and the first attached layer from each other, forming vertical holes by performing a first etch process on the stack layer in a direction from bottom to top, removing the first attached layer, attaching the stack layer in which the vertical holes are formed to the substrate, and performing a second etch process so that each of the vertical holes has a uniform width.

Claims

1. A method of manufacturing a semiconductor memory device, the method comprising:

forming a first attached layer over a first substrate;

forming a stack layer over the first attached layer;

detaching the stack layer from the first attached layer;

performing a first etch process to form a vertical hole in the stack layer in a first direction;

removing the first attached layer;

reversing the stack layer upside down and placing the reversed stack layer over a second substrate; and

performing a second etch process against the reversed stack layer to make the vertical hole have a uniform width.

2. The method of claim 1, wherein the first attached layer includes a porous material.

3. The method of claim 2, wherein the first attached layer includes SiOx, SiNx, amorphous silicon (α

-Si), or an organic layer, where is x is a positive integer.

4. The method of claim 1, wherein the stack layer is formed by stacking an oxide layer and a nitride layer.

5. The method of claim 1, wherein after the stack layer detached from the first attached layer is turned over, the first etch process is performed on the reversed stack layer.

6. The method of claim 1, wherein, before the second etch process, the vertical hole formed in the reversed stack layer has a width larger at a bottom than at a top.

7. The method of claim 1,

wherein the first substrate and the second substrate are the same as each other, and

wherein the placing of the reversed stack layer over the second substrate comprises:

rinsing the first substrate with DI water;

altering a top surface of the first substrate into a hydrophilic surface;

placing the reversed stack layer on the hydrophilic surface; and

performing a heat treatment process against the reversed stack layer.

8. The method of claim 1, further comprising:

forming a second attached layer over the second substrate before placing the reversed stack layer over the second substrate.

9. The method of claim 8, wherein the second attached layer includes silicon-based Pressure Sensitive Adhesive (PSA), acrylate, urethane, or inorganic chelate.

10. The method of claim 1, wherein the first etch process is performed using a first mask pattern, and

wherein the second etch process performed using the first mask pattern.

11. A method of manufacturing a semiconductor memory device, the method comprising:

forming a first attached layer over a first substrate;

forming a stack layer over the first attached layer;

performing a first etch process to form a vertical hole in the stack layer;

detaching the stack layer from the first attached layer;

removing the first attached layer;

reversing the stack layer and attaching the reversed stack layer over a second substrate; and

performing a second etch process against the reversed stack layer to make the vertical hole have a uniform width.

12. The method of claim 11, wherein the first attached layer includes a porous material.

13. The method of claim 12, wherein the first attached layer includes SiOx, SiNx, amorphous silicon (α

-Si), or an organic layer, where is x is a positive integer.

14. The method of claim 11, wherein the stack layer is formed by stacking an oxide layer and a nitride layer.

15. The method of claim 11,

wherein the first substrate and the second substrate are the same as each other, and

wherein the attaching of the reversed stack layer over the second substrate comprises:

rinsing the first substrate with DI water;

altering a top surface of the first substrate into a hydrophilic surface;

placing the reversed stack layer on the hydrophilic surface; and

performing a heat treatment process against the reversed stack layer.

16. The method of claim 11, further comprising:

forming a second attached layer over the second substrate before attaching the reversed stack layer over the second substrate.

17. The method of claim 16, wherein the second attached layer includes silicon-based Pressure Sensitive Adhesive (PSA), acrylate, urethane, or inorganic chelate.

18. The method of claim 11, wherein the first etch process is performed using a first mask pattern;

and

wherein the second etch process is performed using the first mask pattern.