Transistor having reduced channel length

• US 9,281,237 B2
• Filed: 10/01/2012
• Issued: 03/08/2016
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Sylvia, Christina
• Application Number:
  US13/632,761
• Publication Number:
  US 20130092926A1
• Time in Patent Office: 1,254 Days
• Field of Search: 257/392, 257/368, 257/369, 257/412.347, 257/E29.151, 438/275, 438/287, 438/139, 438/151
• US Class Current: 1/1
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A transistor which includes an oxide semiconductor and can operate at high speed is provided. A highly reliable semiconductor device including the transistor is provided. An oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer formed in a groove of a base insulating layer. The channel formation region is embedded in a position overlapping with a gate electrode which has a side surface provided with a sidewall. The groove includes a deep region and a shallow region. The sidewall overlaps with the shallow region, and a connection portion between a wiring and the electrode layer overlaps with the deep region.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an insulating layer over the semiconductor substrate, the insulating layer comprising a groove in which a conductive film comprising a first region and a second region is provided;

an oxide semiconductor film comprising a third region and a fourth region over a top surface of the insulating layer;

a gate insulating layer over the oxide semiconductor film;

a gate electrode over the gate insulating layer, the gate electrode overlapping with the third region; and

a sidewall in contact with a side surface of the gate electrode and a top surface of the gate insulating layer,

wherein the second region is over the first region,

wherein a width of the second region is greater than a width of the first region, and

wherein the fourth region is over and in contact with the second region.

2. The semiconductor device according to claim 1, wherein a conductive layer is in contact with the sidewall and the oxide semiconductor film.

3. The semiconductor device according to claim 1, further comprising:

an interlayer insulating layer over the gate electrode; and

a wiring over the interlayer insulating layer,

wherein the wiring is electrically connected to the conductive film.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor film contains indium, gallium, and zinc.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor film contains indium, tin, and zinc.

6. A semiconductor device comprising:

a semiconductor substrate;

an insulating layer over the semiconductor substrate, the insulating layer comprising a groove in which a conductive film comprising a first region and a second region is provided;

an oxide semiconductor film comprising a third region and a fourth region over a top surface of the insulating layer;

a gate insulating layer over the oxide semiconductor film;

a gate electrode over the gate insulating layer, the gate electrode overlapping with the third region; and

a sidewall in contact with a side surface of the gate electrode and a top surface of the gate insulating layer,

wherein the second region is over the first region,

wherein a width of the second region is greater than a width of the first region,

wherein the fourth region is over and in contact with the second region, and

wherein a top surface of the conductive film is a same as the top surface of the insulating layer.

7. The semiconductor device according to claim 6, wherein a conductive layer is in contact with the sidewall and the oxide semiconductor film.

8. The semiconductor device according to claim 6, further comprising:

an interlayer insulating layer over the gate electrode; and

a wiring over the interlayer insulating layer,

wherein the wiring is electrically connected to the conductive film.

9. The semiconductor device according to claim 6, wherein the oxide semiconductor film contains indium, gallium, and zinc.

10. The semiconductor device according to claim 6, wherein the oxide semiconductor film contains indium, tin, and zinc.