Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods

• US 9,281,241 B2
• Filed: 08/21/2012
• Issued: 03/08/2016
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sulfridge, Marc
• Primary Examiner(s): JUNGE, BRYAN R.
• Application Number:
  US13/590,862
• Publication Number:
  US 20130196501A1
• Time in Patent Office: 1,295 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with terminals of the dies. The first opening separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening. In several embodiments, the method may include constructing an electrically conductive interconnect in at least a portion of the second opening and in electrical contact with the terminal.

Claims

1. A method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies, the individual dies including integrated circuitry and a terminal electrically coupled to the integrated circuitry, the method comprising:

forming a first opening in the substrate from a back side of the substrate toward a front side of the substrate and in alignment with the terminal, the first opening having a generally annular cross-sectional profile and separating an island of substrate material from the substrate;

depositing an insulating material into at least a portion of the first opening, wherein depositing an insulating material comprises at least generally filling the first opening with the insulating material and covering the entire back side of the substrate with the insulating material;

removing at least approximately all the insulating material from the back side of the substrate outside the first opening;

applying a photosensitive polymer material directly onto the back side of the substrate;

forming a second opening in the photosensitive polymer material, wherein the second opening has a diameter less than a diameter of the first opening, and wherein a wall of the second opening is aligned with at least a portion of the insulating material within the first opening; and

removing the island of substrate material after depositing the insulating material and forming a third opening aligned with at least a portion of the terminal, wherein the third opening does not extend completely through the terminal.

2. The method of claim 1, further comprising constructing an electrically conductive interconnect in at least a portion of the third opening and in electrical contact with the terminal.

3. The method of claim 1 wherein depositing an insulating material into at least a portion of the first opening comprises depositing a polymer material into the first opening.

4. The method of claim 3 wherein depositing an insulating material into at least a portion of the first opening comprises depositing a filled epoxy material into the first opening.

5. The method of claim 1 wherein depositing an insulating material into at least a portion of the first opening comprises depositing a polymer material having a coefficient of thermal expansion (CTE) at least generally similar to the CTE of the substrate.

6. The method of claim 1 wherein the substrate further comprises a dielectric layer between the terminal and the front side of the substrate, and wherein:

forming a first opening in the substrate comprises forming a blind hole in the substrate from the back side of the substrate to the dielectric layer; and

removing the island of substrate material to form a third opening in alignment with the terminal further comprises removing at least a portion of the dielectric layer after removing the island of substrate material to expose at least a portion of the terminal.

7. The method of claim 1 wherein removing the island of substrate material comprises removing the island with a wet etching process.

8. The method of claim 1 wherein forming a first opening in the substrate comprises:

applying and patterning a mask layer on the back side of the substrate and forming a first mask layer opening in the mask layer, wherein the first mask layer opening is an annulus aligned with the terminal and having an outer periphery portion inboard of an outer periphery portion of the corresponding terminal;

etching the back side of the substrate with a first etching process to form the first opening in the substrate from the back side of the substrate toward the front side, wherein the first opening has a cross-sectional profile at least approximately identical to the cross-sectional profile of the first mask layer opening; and

removing the mask layer from the back side of the substrate before depositing the insulating material into at least a portion of the first opening.

9. The method of claim 1, further comprising:

adhesively attaching the front side of the substrate to a support member;

removing material from back side of the substrate to thin the substrate before forming the first opening; and

removing the substrate from the support member after constructing the electrically conductive interconnect.

10. The method of claim 1 wherein:

forming a first opening in the substrate comprises forming a plurality of first openings in the back side of each die and in alignment with corresponding terminals, wherein the first openings are generally circular rings surrounding a core of substrate material, and wherein the first openings do not extend through the terminals;

depositing an insulating material comprises disposing a polymeric dielectric material in the first openings; and

removing the island of substrate material comprises removing the cores of substrate material within the first openings after disposing the polymeric dielectric material in the first openings, wherein removing the cores of substrate material forms a plurality of blind vias in alignment with corresponding terminals.

11. The method of claim 10, further comprising planarizing the back side of the dies to remove the dielectric material outside of the openings after filling the openings with the dielectric material.

12. The method of claim 1 wherein forming a first opening in the substrate from a back side of the substrate toward a front side of the substrate and in alignment with the terminal comprises forming the first opening with an outer periphery inboard of a periphery portion of the terminal.

13. A method of processing a semiconductor substrate including a via site and a plug site within the via site, the method comprising:

masking the plug site and a region at least partially surrounding the via site at a back side of the substrate, wherein masking includes exposing a perimeter of the via site;

etching the substrate after masking and defining a plug at the plug site, wherein the plug is at least partially aligned with an electrical contact on the substrate, and wherein etching the substrate after masking defines a plug having an elevation extending generally as high as an elevation of the region;

dispensing a first insulation onto the substrate, over the plug, and between the plug and the substrate;

exposing the plug after dispensing the first insulation;

dispensing a volume of a second insulation directly onto the back side of the substrate after exposing the plug,

wherein dispensing the volume of second insulation comprises dispensing a photosensitive polymer material directly onto the back side of the substrate, and

wherein the volume of second insulation dispensed onto the back side of the substrate covers at least a portion of the first insulation;

patterning the second insulation such that at least a first portion of the first insulation remains covered, at least a second portion of the first insulation is exposed and an exterior surface of the plug is exposed; and

removing the plug.

14. The method of claim 13 wherein removing the plug forms a blind hole, and wherein the method further comprises depositing an electrically conductive fill material into the blind hole and in electrical communication with the electrical contact on the substrate.

15. The method of claim 14 wherein the electrically conductive fill material is deposited into the blind hole using an electroless or electroplating process.

16. The method of claim 14 wherein the electrically conductive fill material is deposited into the blind hole using a solder wave process.

17. The method of claim 14 wherein depositing an electrically conductive fill material into the blind hole comprises depositing the electrically conductive fill material only on sidewalls of the blind hole, and wherein the conductive fill material does not completely fill the blind hole.