CMOS gate stack structures and processes

• US 9,281,248 B1
• Filed: 04/30/2014
• Issued: 03/08/2016
• Est. Priority Date: 06/06/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Hoffmann, Thomas, Ranade, Pushkar, Thompson, Scott E.
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Kilpatrick, Warren H
• Application Number:
  US14/266,115
• Time in Patent Office: 678 Days
• Field of Search: 257/369, 257/372, 438/199, 438/217
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

Claims

1. A method of fabricating a semiconductor device comprising:

providing a substrate having a surface comprising silicon, the surface having formed therein a plurality of device regions comprising a first active region for a SRAM device, a second active region for the SRAM device, a third active region for a logic device, and a fourth active region for the logic device, the first active region comprising a first substantially undoped layer at the surface and a first highly doped p-type conductivity screening layer beneath the first substantially undoped layer, the second active region comprising a second substantially undoped layer at the surface and a second highly doped n-type conductivity screening layer beneath the second substantially undoped layer, the third active region comprising a doped p-type conductivity region extending from the surface, and the fourth active region comprising a layer of an alloy of silicon and germanium at the surface and a doped n-type conductivity region beneath the layer of the alloy of silicon and germanium,

forming one of a first gate stack or a second gate stack in each of the first active region, the second active region, the third active region, and the fourth active region,

wherein the first gate stack comprises at least one gate dielectric layer and at least one metal layer, and wherein the second gate stack comprises at least one gate dielectric layer, and at least one metal layer,

wherein each of first and second gate stacks are of substantially mid-gap workfunctions.

2. The method of claim 1, further comprising selecting the first gate stack for the third active region and selecting the second gate stack for the first active region, the second active region, and the fourth active region.

3. The method of claim 1, wherein the at least one metal layer has a workfunction that is substantially midgap with respect to the first semiconductor material.

4. The method of claim 1, wherein the gate dielectric layer comprises a high-K dielectric layer.

5. The method of claim 1, further comprising providing a halo implant in the third active region and the fourth active region and not in the first active region or the second active region.

6. The method of claim 1, wherein a thickness of the metal layer in the third active region is equal to a thickness of the metal layer in the fourth active region.

7. The method of claim 1, wherein the workfunction of the first gate stack in the third active region and the workfunction of the second gate stack in the fourth active region are equal in value.

8. A method of fabricating an integrated circuit comprising:

providing a substrate having a surface comprising a semiconductor material, the surface having formed therein a plurality of device regions comprising a first active region for a SRAM device, a second active region for the SRAM device, a third active region for a logic device, and a fourth active region for the logic device, the first active region comprising a first substantially undoped layer at the surface and a first highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, the second active region comprising a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer, the third active region comprising a third substantially undoped layer at the surface and a third highly doped screening layer of a first conductivity type beneath the third substantially undoped layer, and the fourth active region comprising a fourth substantially undoped layer at the surface and a fourth highly doped screening layer of a second conductivity type beneath the fourth substantially undoped layer;

forming shallow trench isolation regions separating the plurality of device regions; and

after the forming of the shallow trench isolation regions,

forming at least one gate dielectric layer over the surface,

forming a layer of a first metal over the dielectric layer, the first metal having a workfunction that is substantially midgap with respect to the semiconductor material, and

forming a gate stack having a workfunction that is substantially midgap with respect to the semiconductor material in each of the first active region, the second active region, the third active region, and the fourth active region, comprising the at least one gate dielectric layer and the layer of the first metal.

9. The method of claim 8, further comprising:

prior to the forming of the layer of the first metal, providing at least one of a first capping layer for the first region and a second capping layer for the second region, wherein the first capping layer and the second capping layer are selected to adjust the workfunction of the first metal.

10. The method of claim 8, wherein the first metal is formed over a first region of the dielectric layer corresponding to the first active area, and wherein the method further comprises:

forming a layer of a second metal over a second region of the dielectric layer corresponding to the second active area, the second metal having a workfunction that is substantially midgap with respect to the semiconductor material,

wherein the workfunction of the first metal and the workfunction of the second metal are not equal in value.

11. The method of claim 8, wherein the at least one gate dielectric layer comprises a high-K dielectric layer, and wherein the first metal comprises at least one of TiN, TaN, WN, Al, Ti, or any alloys thereof.

12. The method of claim 8, wherein the semiconductor material comprises silicon, wherein the plurality of regions further comprises a third active region having a doping of the first conductivity type and a fourth active region having doping of the second conductivity type, and wherein the method further comprises:

prior to the forming of the at least one gate dielectric layer, forming a layer of an alloy of silicon and germanium at the surface in at least one of the third active region and the fourth active region.

13. The method of claim 12, further comprising:

removing a portion of the layer of the first metal corresponding to at least one of the first active region, the second active region, or the third active region;

forming a capping layer; and

forming a layer of a second metal over the capping layer.

14. The method of claim 12, further comprising providing a halo implant in the third active region and the fourth active region and not in the first active region or the second active region.

15. The method of claim 8, wherein a thickness of the layer of the first metal in the third active region is equal to a thickness of the layer of the first metal in the fourth active region.

16. The method of claim 8, wherein the workfunction of the gate stack in the third active region and the workfunction of the gate stack in the fourth active region are equal in value.

17. A method of fabricating a semiconductor device comprising:

providing a substrate having a surface comprising a semiconductor material, the surface having formed therein a plurality of shallow trench isolation regions defining a plurality of device regions;

introducing dopants into the plurality of device regions to define at least a first active region for a SRAM device, a second active region for the SRAM device, a third active region for a logic device, and a fourth active region for the logic device, the first active region comprising a first substantially undoped layer at the surface and a first highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, the second active region comprising a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer, the third active region comprising a third substantially undoped layer at the surface and a third highly doped screening layer of a first conductivity type beneath the third substantially undoped layer, and the fourth active region comprising a fourth substantially undoped layer at the surface and a fourth highly doped screening layer of a second conductivity type beneath the fourth substantially undoped layer; and

after the introducing of the dopants into the plurality of device regions,

forming at least one gate dielectric layer over the surface,

forming a layer of a first metal over the dielectric layer, the first metal having a workfunction that is substantially midgap with respect to the semiconductor material, and

forming a gate stack having a workfunction that is substantially midgap with respect to the semiconductor material in each of the first active region, the second active region, the third active region, and the fourth active region, comprising the at least one gate dielectric layer and the layer of the first metal.

18. The method of claim 17, further comprising:

prior to the forming of the layer of the first metal, providing at least one of a first capping layer for the first region and a second capping layer for the second region, wherein the first capping layer and the second capping layer are selected to adjust the workfunction of the first metal.

19. The method of claim 17, wherein the first metal is formed over a first region of the dielectric layer corresponding to the first active area, and wherein the method further comprises:

forming a layer of a second metal over a second region of the dielectric layer corresponding the second active area, the second metal having a workfunction that is substantially midgap with respect to the semiconductor material,

wherein the workfunction of the first metal and the workfunction of the second metal are not equal in value.

20. The method of claim 17, wherein the at least one gate dielectric layer comprises a high-K dielectric layer, and wherein the first metal comprises at least one of TiN, TaN, WN, Al, Ti, or any alloys thereof.

21. The method of claim 17, wherein the semiconductor material comprises silicon, wherein the introducing of the dopants into the plurality of device regions further defines a third active region having a doping of the first conductivity type and a fourth active region having doping of the second conductivity type, and wherein the method further comprises:

prior to the forming of the at least one gate dielectric layer, forming a layer of an alloy of silicon and germanium at the surface in at least one of the third active region and the fourth active region.

22. The method of claim 21, further comprising:

removing a portion of the layer of the first metal corresponding to at least one of the first active region, the second active region, or the third active region;

forming a capping layer; and

forming a layer of a second metal over the capping layer.

23. The method of claim 21, further comprising providing a halo implant in the third active region and the fourth active region and not in the first active region or the second active region.

24. The method of claim 17, wherein a thickness of the layer of the first metal in the third active region is equal to a thickness of the layer of the first metal in the fourth active region.

25. The method of claim 17, wherein the workfunction of the gate stack in the third active region and the workfunction of the gate stack in the fourth active region are equal in value.