Microelectronic packages having texturized solder pads and methods for the fabrication thereof

• US 9,281,286 B1
• Filed: 08/27/2014
• Issued: 03/08/2016
• Est. Priority Date: 08/27/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Yap, Weng F., Magnus, Alan J.
• Primary Examiner(s): Stultz, Jessica
• Assistant Examiner(s): Vu, Vu A
• Application Number:
  US14/470,679
• Publication Number:
  US 20160064341A1
• Time in Patent Office: 559 Days
• Field of Search: 438/106
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/03466 Conformal deposition, i.e. blanket deposition of a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05105 Gallium [Ga] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/2105 : Shape
• CPC Class Codes: H01L 2224/215 : Material
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.

Claims

1. A method for fabricating a microelectronic package, comprising:

photolitographically patterning an under-pad dielectric layer to create a texturized dielectric region having a texture pattern and to create via openings extending through the under-pad dielectric layer; and

producing a texturized solder pad over the texturized dielectric region, the texturized solder pad having a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions;

wherein the patterning comprises;

treating the region of the under-pad dielectric layer in which the texture pattern is formed with ultraviolet (UV) light at a first predetermined dosage;

treating the regions of the under-pad dielectric layer in which the via openings are formed with UV light at a second predetermined dosage greater than the first predetermined dosage; and

developing the under-pad dielectric layer to simultaneously form the via openings and the texture pattern.

2. The method of claim 1 wherein forming comprises forming the texturized dielectric region such that the texture pattern has a maximum feature depth less than the thickness of the under-pad dielectric layer.

3. The method of claim 1 wherein forming comprises photolitographically patterning the under-pad dielectric layer to create the texturized dielectric region therein.

4. The method of claim 3 wherein producing comprises:

depositing a metal level over the under-pad dielectric layer after patterning thereof; and

patterning the metal level to define the texturized solder pad and at least one interconnect line electrically coupled to the texturized solder pad.

5. The method of claim 4 wherein the interconnect line has an average thickness, wherein the texture pattern is produced to have a minimum feature width, and wherein the minimum feature width of the texture pattern is at least twice the average thickness of the interconnect line.

6. The method of claim 1 further comprising:

depositing a solder mask layer over the texturized solder pad;

forming a solder mask opening in the solder mask exposing the texturized solder pad; and

forming a solder contact over the solder mask opening and bonded to the texturized solder pad.

7. The method of claim 1 wherein depositing comprises depositing the under-pad dielectric layer over a molded panel in which at least one semiconductor die has been embedded, and wherein the texturized dielectric region and the texturized solder pads are formed at locations laterally outboard of the semiconductor die.

8. The method of claim 1 wherein the texture pattern is formed to have a maximum feature depth less than the depth of the via openings.

9. The method of claim 1 further comprising depositing the under-pad dielectric layer over a base dielectric layer such that an interlayer juncture is produced therebetween, the texture pattern formed to extend through the under-pad dielectric layer and to terminate substantially at the interlayer juncture.

10. A method for fabricating a microelectronic package, comprising:

depositing a photoimagable dielectric layer over a semiconductor die;

photolitographically patterning the photoimagable dielectric layer to define texturized dielectric regions at selected locations across the first photoimagable dielectric layer and to further define via openings at different locations across the first photoimagable dielectric layer, the texturized dielectric regions having a maximum feature depth less than the depth of the via openings as taken from an upper surface of the photoimagable dielectric layer;

producing a patterned metal level over the photoimagable dielectric layer, the patterned metal level produced to include (i) texturized solder pads formed over the texturized dielectric regions, and (ii) interconnect lines electrically coupling the solder pads to the semiconductor die;

forming a solder mask layer having solder mask openings through which the texturized solder pads are exposed; and

forming solder contacts in the solder mask openings and bonded to the texturized solder pads.

11. The method of claim 10 wherein the semiconductor die is embedded is a molded panel along with a number of other semiconductor die, wherein the photoimagable dielectric layer is deposited over the molded panel, and wherein the method further comprises singulating the molded panel after forming the solder contacts to produce a plurality of Fan-Out Wafer Level Packages.

12. The method of claim 10 wherein photolitographically patterning comprises photolitographically patterning the photoimagable dielectric layer to impart the texturized dielectric regions with hatch patterns.

13. The method of claim 10 further comprising depositing the photoimagable dielectric layer over a base dielectric layer such that an interlayer juncture is produced therebetween, the texture pattern formed to extend through the photoimagable dielectric layer and to terminate substantially at the interlayer juncture.

14. A microelectronic package, comprising:

a first photoimagable dielectric layer in which a texturized dielectric region having a texture pattern is formed, the first photoimagable dielectric layer having a thickness greater than a maximum feature depth of the texture pattern;

a texturized solder pad overlying the texturized dielectric region and having a solder contact surface, the texturized solder pad substantially conformal with the texturized dielectric region such that the texture pattern is transferred to the solder contact surface;

a solder contact overlying the texturized solder pad and bonded to the solder contact surface;

a semiconductor die; and

a molded package body having a fan-out region extending around the semiconductor die, the texturized dielectric region located over the fan-out region.

15. The microelectronic package of claim 14 further comprising:

a semiconductor die having a bond pad;

a photoimagable dielectric layer in which the texturized dielectric region is formed; and

an interconnect line overlying the photoimagable dielectric layer and electrically coupling the bond pad to the texturized solder pad.

16. The microelectronic package of claim 14 further comprising a base photoimagable dielectric layer underlying the first photoimagable dielectric layer and forming an interlayer juncture therewith, the texture pattern of the texturized dielectric region extending to and terminating at the interlayer juncture.

17. The microelectronic package of claim 16 further comprising a via extending through the first photoimagable dielectric layer and through the base photoimagable dielectric layer, the via formed at a location offset from the texturized solder pad and having a depth greater than the maximum feature depth of the texture pattern.

18. The microelectronic package of claim 14 wherein the texture pattern comprises a plurality of channels that are formed in, but do not penetrate through the texturized dielectric region.

19. A microelectronic package, comprising:

a first photoimagable dielectric layer in which a texturized dielectric region having a texture pattern is formed, the first photoimagable dielectric layer having a thickness greater than a maximum feature depth of the texture pattern;

a texturized solder pad overlying the texturized dielectric region and having a solder contact surface, the texturized solder pad substantially conformal with the texturized dielectric region such that the texture pattern is transferred to the solder contact surface;

a solder contact overlying the texturized solder pad and bonded to the solder contact surface;

a semiconductor die having a bond pad;

a photoimagable dielectric layer in which the texturized dielectric region is formed; and

an interconnect line overlying the photoimagable dielectric layer and electrically coupling the bond pad to the texturized solder pad;

wherein the interconnect line has an average thickness, and wherein the texturized dielectric region has a minimum feature width greater than twice the average thickness of the interconnect line.

20. The microelectronic package of claim 19 further comprising a base photoimagable dielectric layer underlying the first photoimagable dielectric layer and forming an interlayer juncture therewith, the texture pattern of the texturized dielectric region extending to and terminating at the interlayer juncture.