Memory structure and method for manufacturing the same

• US 9,281,315 B1
• Filed: 03/03/2015
• Issued: 03/08/2016
• Est. Priority Date: 03/03/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Yeh, Teng-Hao, Shih, Yen-Hao, Hu, Chih-Wei
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Budd, Paul
• Application Number:
  US14/636,261
• Time in Patent Office: 371 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A memory structure and a method for manufacturing the same are provided. The memory structure comprises a substrate, stacks, memory layers, a conductive material and conductive lines. The stacks are positioned on the substrate. The stacks are separated from each other by trenches. Each of the stacks comprises alternately stacked conductive stripes and insulating stripes. The memory layers conformally cover the stacks respectively. The conductive material is positioned in the trenches and on the stacks. The conductive material in the trenches forms one or more holes in each of the trenches. The conductive lines are positioned on the conductive material. Each of the conductive lines comprises a first portion and a second portion connected to each other, the first portion extends along a direction perpendicular to an extending direction of the stacks, and the second portion extends along the extending direction of the stacks.

Claims

1. A method for manufacturing a memory structure, comprising:

forming a plurality of stacks on a substrate, wherein the stacks are separated from each other by a plurality of trenches, and each of the stacks comprises alternately stacked conductive stripes and insulating stripes;

forming a plurality of memory layers conformally covering the stacks respectively;

forming a conductive material in the trenches and on the stacks, the conductive material having a top portion;

forming one or more holes in the conductive material in each of the trenches; and

defining a plurality of predetermined regions for respectively forming a plurality of conductive lines in the top portion of the conductive material, wherein each of the predetermined regions comprises a first predetermined region and a second predetermined region connected to each other, the first predetermined region extends along a direction perpendicular to an extending direction of the stacks, and the second predetermined region extends along the extending direction of the stacks.

2. The method according to claim 1, wherein the one or more holes in each of the trenches are arranged in a matrix, or arranged to constitute a triangle-like in layout design.

3. The method according to claim 1, wherein said defining the predetermined regions is carried out before said forming the one or more holes.

4. The method according to claim 1, wherein said defining the predetermined regions is carried out after said forming the one or more holes.

5. The method according to claim 1, wherein lengths of the first predetermined regions and the second predetermined regions are sequentially increased.

6. The method according to claim 1, further comprises:

removing the top portion of the conductive material that is not in the predetermined regions; and

forming the conductive lines on the top portion of the conductive material remained in the predetermined regions.

7. The method according to claim 6, further comprises:

before said removing the top portion of the conductive material that is not in the predetermined regions, filling an insulating material into the one or more holes in each of the trenches.

8. The method according to claim 7, wherein said removing the top portion of the conductive material that is not in the predetermined regions comprises a cutting step and a removing step, the cutting step comprises removing portions of the top portion of conductive material and portions of the memory layers on the stacks along the direction perpendicular to the extending direction of the stacks, and the removing step comprises removing remained portions of the top portion of conductive material that is not in the predetermined regions.

9. The method according to claim 6, wherein the first predetermined regions of adjacent two of the predetermined regions are connected to each other by an extending portion of the second predetermined region of one of the adjacent two of the predetermined regions, and the top portion of the conductive material in the extending portion is removed by a cutting step.

10. The method according to claim 6, wherein the first predetermined regions of adjacent two of the predetermined regions are connected to each other by an extending portion of the second predetermined region of one of the adjacent two of the predetermined regions and an extending portion of the second predetermined region of another one of the predetermined regions, and the top portion of the conductive material in the extending portion of the second predetermined region of one of the adjacent two of the predetermined regions and in the extending portion of the second predetermined region of the another one of the predetermined regions is removed by a cutting step.

11. The method according to claim 1, wherein the conductive lines are formed of silicide.

12. The method according to claim 1, wherein the conductive stripes in the stacks are used as bit lines, and the conductive lines are used as word lines.

13. The method according to claim 1, wherein the conductive stripes in the stacks are used as word lines, and the conductive lines are used as bit lines.

14. A memory structure, comprising:

a substrate;

a plurality of stacks positioned on the substrate, wherein the stacks are separated from each other by a plurality of trenches, and each of the stacks comprises alternately stacked conductive stripes and insulating stripes;

a plurality of memory layers conformally covering the stacks respectively;

a conductive material positioned in the trenches and on the stacks, wherein the conductive material in the trenches forms one or more holes in each of the trenches; and

a plurality of conductive lines positioned on the conductive material, wherein each of the conductive lines comprises a first portion and a second portion connected to each other, the first portion extends along a direction perpendicular to an extending direction of the stacks, and the second portion extends along the extending direction of the stacks.

15. The memory structure according to claim 14, wherein the one or more holes in each of the trenches are arranged in a matrix.

16. The memory structure according to claim 14, wherein the one or more holes in each of the trenches are arranged to constitute a triangle-like in layout design.

17. The memory structure according to claim 14, wherein lengths of the first portions and the second portions of the conductive lines are sequentially increased.

18. The memory structure according to claim 14, wherein the conductive lines are formed of silicide.

19. The memory structure according to claim 14, wherein the conductive stripes in the stacks are used as bit lines, and the conductive lines are used as word lines.

20. The memory structure according to claim 14, wherein the conductive stripes in the stacks are used as word lines, and the conductive lines are used as bit lines.