Circuits using gate-all-around technology
First Claim
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1. A semiconductor structure, comprising:
- a first gate-all-around (GAA) structure configured to form a first circuit;
a second GAA structure configured to form a second circuit similar to the first circuit;
whereineach of the first GAA structure and the second GAA structure comprises;
at least one GAA device, each GAA device comprising;
at least one nanowire;
a first oxide diffusion (OD) region and a second OD region connected to opposite ends of the at least one nanowire; and
a gate region wrapping all around a portion of each of the at least one nanowire;
at least one first OD region contact element, each first OD region contact element electrically coupled to a corresponding first OD region of the at least one GAA device; and
at least one second OD region contact element, each second OD region contact element electrically coupled to a corresponding second OD region of the at least one GAA device; and
the first GAA structure and the second GAA structure have substantially a same of at least one of the following features;
a number of GAA devices in the at least one GAA device configured to have current flows from the first OD region to the second OD region;
a number of GAA devices in the at least one GAA device configured to have current flows from the second OD region to the first OD region;
a number of integral first OD region of the at least one GAA device;
a number of integral second OD region of the at least one GAA device;
an orientation of and a corresponding direction of current flow through the first GAA structure or the second GAA structure;
a number of the at least one first OD region contact element;
an orientation of the at least one first OD region contact element;
a number of the at least one second OD region contact element;
an orientation of the at least one second OD region contact element;
a number of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure;
a number of rows of the at least one nanowire arranged in an array for each corresponding GAA devices of the first GAA structure and the second GAA structure;
a number of nanowires in a row of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure;
a number of columns of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure;
a number of nanowires in a column of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure; and
a shape of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure.
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Abstract
A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.
6 Citations
24 Claims
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1. A semiconductor structure, comprising:
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a first gate-all-around (GAA) structure configured to form a first circuit; a second GAA structure configured to form a second circuit similar to the first circuit; wherein each of the first GAA structure and the second GAA structure comprises; at least one GAA device, each GAA device comprising; at least one nanowire; a first oxide diffusion (OD) region and a second OD region connected to opposite ends of the at least one nanowire; and a gate region wrapping all around a portion of each of the at least one nanowire; at least one first OD region contact element, each first OD region contact element electrically coupled to a corresponding first OD region of the at least one GAA device; and at least one second OD region contact element, each second OD region contact element electrically coupled to a corresponding second OD region of the at least one GAA device; and the first GAA structure and the second GAA structure have substantially a same of at least one of the following features; a number of GAA devices in the at least one GAA device configured to have current flows from the first OD region to the second OD region; a number of GAA devices in the at least one GAA device configured to have current flows from the second OD region to the first OD region; a number of integral first OD region of the at least one GAA device; a number of integral second OD region of the at least one GAA device; an orientation of and a corresponding direction of current flow through the first GAA structure or the second GAA structure; a number of the at least one first OD region contact element; an orientation of the at least one first OD region contact element; a number of the at least one second OD region contact element; an orientation of the at least one second OD region contact element; a number of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure; a number of rows of the at least one nanowire arranged in an array for each corresponding GAA devices of the first GAA structure and the second GAA structure; a number of nanowires in a row of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure; a number of columns of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure; a number of nanowires in a column of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA structure and the second GAA structure; and a shape of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor structure, comprising:
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a first gate-all-around (GAA) structure configured to form a first circuit; a second GAA structure configured to form a second circuit similar to the first circuit; wherein each of the first GAA structure and the second GAA structure comprises; at least one GAA device, each GAA device comprising; at least one nanowire; a first oxide diffusion (OD) region and a second OD region connected to opposite ends of the at least one nanowire; and a gate region wrapping all around a portion of each of the at least one nanowire; and the first GAA structure and the second GAA structure are configured such that if a first current path through the first GAA structure is from the first OD region of one end of the at least one GAA device to the second OD region of the other end of the at least one GAA device of the first GAA structure, a second current path through the second GAA structure is from the first OD region of one end of the at least one GAA device to the second OD region of the other end of the at least one GAA device of the second GAA structure, and if the first current path is from the second OD region of the one end of the at least one GAA device to the first OD region of the other end of the at least one GAA device of the first GAA structure, the second current path is from the second OD region of the one end of the at least one GAA device to the first OD region of the other end of the at least one GAA device of the second GAA structure. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A layout for a first gate-all-around (GAA) structure and a second GAA structure configured to form corresponding first circuit and second circuit similar to each other, the layout comprising:
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a first layer comprising at least one first oxide diffusion (OD) region of the first GAA structure and substantially a same number of at least one first OD region of the second GAA structure; a second layer comprising at least one second OD region of the first GAA structure and substantially a same number of at least one second OD region of the second GAA structure; and a third layer comprising for the first GAA structure and the second GAA structure substantially a same of at least one of the following features; a number of at least one nanowire between each corresponding first OD region and second OD region of the first layer and the second layer; a number of rows of the at least one nanowire arranged in an array between each corresponding first OD region and second OD region of the first layer and the second layer; a number of nanowires in a row of the at least one nanowire arranged in the array between each corresponding first OD region and second OD region of the first layer and the second layer; a number of columns of the at least one nanowire arranged in the array between each corresponding first OD region and second OD region of the first layer and the second layer; and a number of nanowires in a column of the at least one nanowire arranged in the array between each corresponding first OD region and second OD region of the first layer and the second layer. - View Dependent Claims (22, 23, 24)
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Specification