Charge compensation structure and manufacturing therefor
First Claim
1. A charge-compensation semiconductor device, comprising:
- a rated breakdown voltage;
a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge;
a source metallization arranged on the first surface; and
a drain metallization arranged opposite to the source metallization,in a vertical cross-section substantially orthogonal to the first surface the semiconductor body further comprising;
an intrinsic semiconductor region arranged in the peripheral area; and
a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area, the first pillar regions having a higher doping concentration than the intrinsic semiconductor region, the first pillar regions being in Ohmic contact with the drain metallization, the second pillar regions of the active area being in Ohmic contact with the source metallization via respective body regions having a higher doping concentration than the second pillar regions, at least a majority of the second pillar regions of the peripheral area adjoining a connecting region which is of the same conductivity type as the second pillar regions and has a lower doping concentration than an adjoining outermost of the body regions, between adjacent first pillar regions and second pillar regions a respective pn-junction being formed, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the intrinsic semiconductor region at a horizontal position where a voltage at the first surface is at least about a fifth of the rated breakdown voltage when the rated breakdown voltage is applied between the source metallization and the drain metallization.
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Accused Products
Abstract
A charge-compensation semiconductor device includes a semiconductor body including a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge, a source metallization arranged on the first surface, and a drain metallization arranged on the drain region and in Ohmic contact with the drain region. In a vertical cross-section substantially orthogonal to the first surface the charge-compensation semiconductor device further includes: an equipotential region in Ohmic contact with the drain metallization and arranged in the peripheral area and next to the first surface, a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants, and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area. The first pillar regions having a second concentration of dopants of the first conductivity type higher than the first concentration and are in Ohmic contact with the drain region. The second pillar regions are of a second conductivity type and in Ohmic contact with the source metallization. At least one of an outermost of the first pillar regions and an outermost of the second pillar regions forms an interface with the low-doped semiconductor region. A horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.
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Citations
20 Claims
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1. A charge-compensation semiconductor device, comprising:
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a rated breakdown voltage; a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge; a source metallization arranged on the first surface; and a drain metallization arranged opposite to the source metallization, in a vertical cross-section substantially orthogonal to the first surface the semiconductor body further comprising; an intrinsic semiconductor region arranged in the peripheral area; and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area, the first pillar regions having a higher doping concentration than the intrinsic semiconductor region, the first pillar regions being in Ohmic contact with the drain metallization, the second pillar regions of the active area being in Ohmic contact with the source metallization via respective body regions having a higher doping concentration than the second pillar regions, at least a majority of the second pillar regions of the peripheral area adjoining a connecting region which is of the same conductivity type as the second pillar regions and has a lower doping concentration than an adjoining outermost of the body regions, between adjacent first pillar regions and second pillar regions a respective pn-junction being formed, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the intrinsic semiconductor region at a horizontal position where a voltage at the first surface is at least about a fifth of the rated breakdown voltage when the rated breakdown voltage is applied between the source metallization and the drain metallization. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
a drain region adjoining the drain metallization at a second surface of the semiconductor body, in Ohmic contact with the first pillar regions and having a higher doping than the first pillar regions, and an equipotential region which is in Ohmic contact with the drain metallization and arranged next to the edge and the first surface, wherein a horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.
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7. The charge-compensation semiconductor device of claim 6, wherein the equipotential region comprises at least one of a field plate arranged on the first surface, and a field-stopper region adjoining the intrinsic semiconductor region and having a higher average concentration of dopants of the first conductivity type than the intrinsic semiconductor region.
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8. The charge-compensation semiconductor device of claim 6, wherein the connecting region extends at least close to the field-stopper region.
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9. The charge-compensation semiconductor device of claim 1, wherein the doping concentration of the first pillar regions is at least about ten times a doping concentration of the intrinsic semiconductor region.
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10. The charge-compensation semiconductor device of claim 1, wherein at least one of the second pillar regions in the peripheral area substantially extends into the same depth as the second pillar regions in the active area.
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11. The charge-compensation semiconductor device of claim 1, wherein a vertical extension of at least one of the second pillar regions in the peripheral area is lower than a vertical extension of the second pillar regions in the active area.
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12. The charge-compensation semiconductor device of claim 1, wherein a doping concentration of at least one of the second pillar regions in the peripheral area differs from a doping concentration of the second pillar regions in the active area.
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13. The charge-compensation semiconductor device of claim 1, further comprising a depletable semiconductor region arranged between the connecting region and the first surface, forming a pn-junction with the connecting region, having a higher doping concentration than the intrinsic semiconductor region.
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14. A charge-compensation semiconductor device, comprising:
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a semiconductor body comprising a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge; a source metallization arranged on the first surface; and a drain metallization arranged on the drain region and in Ohmic contact with the drain region, in a vertical cross-section substantially orthogonal to the first surface the charge-compensation semiconductor device further comprising; an equipotential region in Ohmic contact with the drain metallization and arranged in the peripheral area and next to the first surface; a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants; and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area, the first pillar regions having a second concentration of dopants of the first conductivity type higher than the first concentration of dopants, the first pillar regions being in Ohmic contact with the drain region, the second pillar regions being of a second conductivity type and in Ohmic contact with the source metallization, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the low-doped semiconductor region, wherein a horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3. - View Dependent Claims (15, 16, 17, 18)
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19. A method for manufacturing a charge-compensation semiconductor device, the method comprising:
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providing a semiconductor body comprising a first surface, a second surface arranged opposite to the first surface, a drain region of a first conductivity type extending to the second surface, an active area, and a peripheral area surrounding the active area; in a vertical cross-section substantially orthogonal to the first surface the semiconductor body comprising; a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants; and a plurality of first pillar regions alternating with second pillar regions in the active area and in the peripheral area, the first pillar regions having a second concentration of dopants of a first conductivity type higher than the first concentration of dopants, between adjoining first pillar regions and second pillar regions a respective pn-junction being formed, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the low-doped semiconductor region; and a connecting region of the second conductivity type arranged in the peripheral area and adjoining at least a majority of the second pillar regions of the peripheral area, the method further comprising; forming in the peripheral area an equipotential structure at least next to the first surface; forming a source metallization on the first surface in Ohmic contact with the second pillar regions of the active area and with the connecting region; forming a drain metallization opposite to the source metallization and in Ohmic contact with the equipotential structure and the first pillar regions; and cutting the semiconductor body to form an edge extending between the first surface and the second surface and surrounding the active area, such that a horizontal distance between the interface and the equipotential structure divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3. - View Dependent Claims (20)
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Specification