Charge compensation structure and manufacturing therefor

• US 9,281,392 B2
• Filed: 06/27/2014
• Issued: 03/08/2016
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weyers, Joachim, Willmeroth, Armin
• Primary Examiner(s): AU, BAC H
• Application Number:
  US14/316,987
• Publication Number:
  US 20150380542A1
• Time in Patent Office: 620 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A charge-compensation semiconductor device includes a semiconductor body including a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge, a source metallization arranged on the first surface, and a drain metallization arranged on the drain region and in Ohmic contact with the drain region. In a vertical cross-section substantially orthogonal to the first surface the charge-compensation semiconductor device further includes: an equipotential region in Ohmic contact with the drain metallization and arranged in the peripheral area and next to the first surface, a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants, and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area. The first pillar regions having a second concentration of dopants of the first conductivity type higher than the first concentration and are in Ohmic contact with the drain region. The second pillar regions are of a second conductivity type and in Ohmic contact with the source metallization. At least one of an outermost of the first pillar regions and an outermost of the second pillar regions forms an interface with the low-doped semiconductor region. A horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.

Claims

1. A charge-compensation semiconductor device, comprising:

a rated breakdown voltage;

a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge;

a source metallization arranged on the first surface; and

a drain metallization arranged opposite to the source metallization,

in a vertical cross-section substantially orthogonal to the first surface the semiconductor body further comprising;

an intrinsic semiconductor region arranged in the peripheral area; and

a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area, the first pillar regions having a higher doping concentration than the intrinsic semiconductor region, the first pillar regions being in Ohmic contact with the drain metallization, the second pillar regions of the active area being in Ohmic contact with the source metallization via respective body regions having a higher doping concentration than the second pillar regions, at least a majority of the second pillar regions of the peripheral area adjoining a connecting region which is of the same conductivity type as the second pillar regions and has a lower doping concentration than an adjoining outermost of the body regions, between adjacent first pillar regions and second pillar regions a respective pn-junction being formed, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the intrinsic semiconductor region at a horizontal position where a voltage at the first surface is at least about a fifth of the rated breakdown voltage when the rated breakdown voltage is applied between the source metallization and the drain metallization.

2. The charge-compensation semiconductor device of claim 1, wherein the interface is formed at a horizontal position where the voltage at the first surface is at least about a third of the rated breakdown voltage when the rated breakdown voltage is applied between the source metallization and the drain metallization;

and/or wherein the interface is formed at a horizontal position where the voltage at the first surface is lower than about four fifths of the rated breakdown voltage when the rated breakdown voltage is applied between the source metallization and the drain metallization.

3. The charge-compensation semiconductor device of claim 1, wherein the peripheral area comprises an outer portion which is devoid of both the first pillar regions and the second pillar regions, and an inner portion arranged between the active area and the outer portion, wherein a boundary between the inner portion and the outer portion of the peripheral area is, in a corner region of the peripheral area next to two adjacent vertical sides of the edge, substantially parallel to one of the two vertical sides or forms an angle of about 60°

, 45°

or 30°

with the edge.

4. The charge-compensation semiconductor device of claim 3, wherein the doping concentration of the first pillar regions is lower in the inner portion of the peripheral area compared to the active area, and/or wherein the doping concentration of the second pillar regions is lower in the inner portion of the peripheral area compared to the active area.

5. The charge-compensation semiconductor device of claim 1, wherein a horizontal distance between the edge and the interface divided by a horizontal distance between the source metallization and the interface is in a range from about 0.1 to about 0.9.

6. The charge-compensation semiconductor device of claim 1, further comprising at least one of

an equipotential region which is in Ohmic contact with the drain metallization and arranged next to the edge and the first surface, wherein a horizontal distance between the interface and the equipotential region divided by a horizontal distance between the source metallization and the interface is in a range from about 0.2 to about 5;

and

a drain region adjoining the drain metallization at a second surface of the semiconductor body, in Ohmic contact with the first pillar regions and having a higher doping than the first pillar regions, and an equipotential region which is in Ohmic contact with the drain metallization and arranged next to the edge and the first surface, wherein a horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.

7. The charge-compensation semiconductor device of claim 6, wherein the equipotential region comprises at least one of a field plate arranged on the first surface, and a field-stopper region adjoining the intrinsic semiconductor region and having a higher average concentration of dopants of the first conductivity type than the intrinsic semiconductor region.

8. The charge-compensation semiconductor device of claim 6, wherein the connecting region extends at least close to the field-stopper region.

9. The charge-compensation semiconductor device of claim 1, wherein the doping concentration of the first pillar regions is at least about ten times a doping concentration of the intrinsic semiconductor region.

10. The charge-compensation semiconductor device of claim 1, wherein at least one of the second pillar regions in the peripheral area substantially extends into the same depth as the second pillar regions in the active area.

11. The charge-compensation semiconductor device of claim 1, wherein a vertical extension of at least one of the second pillar regions in the peripheral area is lower than a vertical extension of the second pillar regions in the active area.

12. The charge-compensation semiconductor device of claim 1, wherein a doping concentration of at least one of the second pillar regions in the peripheral area differs from a doping concentration of the second pillar regions in the active area.

13. The charge-compensation semiconductor device of claim 1, further comprising a depletable semiconductor region arranged between the connecting region and the first surface, forming a pn-junction with the connecting region, having a higher doping concentration than the intrinsic semiconductor region.

14. A charge-compensation semiconductor device, comprising:

a semiconductor body comprising a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge;

a source metallization arranged on the first surface; and

a drain metallization arranged on the drain region and in Ohmic contact with the drain region,

in a vertical cross-section substantially orthogonal to the first surface the charge-compensation semiconductor device further comprising;

an equipotential region in Ohmic contact with the drain metallization and arranged in the peripheral area and next to the first surface;

a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants; and

a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area, the first pillar regions having a second concentration of dopants of the first conductivity type higher than the first concentration of dopants, the first pillar regions being in Ohmic contact with the drain region, the second pillar regions being of a second conductivity type and in Ohmic contact with the source metallization, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the low-doped semiconductor region, wherein a horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.

15. The charge-compensation semiconductor device of claim 14, further comprising at least one of a first depletable semiconductor region of the second conductivity type connecting at least the majority of the second pillar regions of the peripheral area, a second depletable semiconductor region of the first conductivity type having a concentration of dopants higher than the first concentration of dopants and arranged between the first depletable semiconductor region and the first surface, and a plurality of body regions of the second conductivity type, each of the body regions having in the active area a higher doping concentration than an adjoining second pillar region and an outermost of the body regions having a higher doping concentration than the adjoining first depletable semiconductor region.

16. The charge-compensation semiconductor device of claim 14, wherein the equipotential region comprises at least one of a field plate arranged on the first surface, a field-stopper region of the first conductivity type adjoining the low-doped semiconductor region and having a concentration of dopants higher than the first concentration of dopants, and a poly-silicon region arranged between the field plate and the field-stopper region.

17. The charge-compensation semiconductor device of claim 14, wherein the low-doped semiconductor region has a maximum doping concentration of less than about 10¹⁵ cm⁻

3.

18. The charge-compensation semiconductor device of claim 14, wherein the interface is formed at a horizontal position where a voltage at the first surface is at least about a fifth of a rated breakdown voltage of the charge-compensation semiconductor device when the rated breakdown voltage is applied between the source metallization and the drain metallization.

19. A method for manufacturing a charge-compensation semiconductor device, the method comprising:

providing a semiconductor body comprising a first surface, a second surface arranged opposite to the first surface, a drain region of a first conductivity type extending to the second surface, an active area, and a peripheral area surrounding the active area;

in a vertical cross-section substantially orthogonal to the first surface the semiconductor body comprising;

a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants; and

a plurality of first pillar regions alternating with second pillar regions in the active area and in the peripheral area, the first pillar regions having a second concentration of dopants of a first conductivity type higher than the first concentration of dopants, between adjoining first pillar regions and second pillar regions a respective pn-junction being formed, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the low-doped semiconductor region; and

a connecting region of the second conductivity type arranged in the peripheral area and adjoining at least a majority of the second pillar regions of the peripheral area,

the method further comprising;

forming in the peripheral area an equipotential structure at least next to the first surface;

forming a source metallization on the first surface in Ohmic contact with the second pillar regions of the active area and with the connecting region;

forming a drain metallization opposite to the source metallization and in Ohmic contact with the equipotential structure and the first pillar regions; and

cutting the semiconductor body to form an edge extending between the first surface and the second surface and surrounding the active area,

such that a horizontal distance between the interface and the equipotential structure divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.

20. The method of claim 19, wherein providing the semiconductor body comprises at least one of:

defining the active area;

defining an outer portion of the peripheral area and an inner portion of the peripheral area, the inner portion being arranged between the active area and the outer portion, such that an outer boundary of the outer portion is substantially rectangular and that a boundary between the inner portion and the outer portion of the peripheral area is next to a corner of the outer boundary substantially parallel to a line segment of the outer boundary or forms an angle of about 60°

, about 45°

or about 30°

with the line segment when seen form above;

forming the first pillar regions using a first mask comprising first openings extending, in a first horizontal direction, from the active area into the inner portion; and

forming the second pillar regions using a second mask comprising second openings extending, in the first horizontal direction, from the active area into the inner portion, wherein a horizontal extension of the first openings in a second horizontal direction substantially orthogonal to the first horizontal direction is larger in the active area compared to the inner portion, and/or wherein a horizontal extension in the second horizontal direction of the second openings is larger in the active area compared to the inner portion; and

forming the first pillar regions with a reduced doping concentration in the inner portion of the peripheral area compared to the active area and forming the second pillar regions with a reduced doping concentration in the inner portion of the peripheral area compared to the active area such that the first pillar regions and the second pillar regions are substantially parallel to each other and that a boundary between the inner portion and the outer portion of the peripheral area is, in a corner region where two vertical sides of the edge approach, substantially parallel to one of the two vertical sides or forms an angle of about 60°

, 45°

or 30°

with the edge.