Semiconductor device and method for manufacturing the same

• US 9,281,405 B2
• Filed: 07/22/2014
• Issued: 03/08/2016
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasagawa, Shinya, Suzawa, Hideomi
• Primary Examiner(s): Blum, David S
• Application Number:
  US14/337,583
• Publication Number:
  US 20140332801A1
• Time in Patent Office: 595 Days
• Field of Search: 257/43
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer over the gate insulating layer;

a first conductive layer over the semiconductor layer;

a second conductive layer over the first conductive layer;

a first insulating layer over the second conductive layer; and

a hard mask layer over the first insulating layer,

wherein the hard mask layer comprises an opening which overlaps with a channel formation region of the semiconductor layer.

2. The semiconductor device according to claim 1,

wherein the semiconductor layer includes an oxide including In, an element M, and Zn, and

wherein the element M is at least one element selected from the group consisting of Ga, Sn, Hf, Al, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

3. The semiconductor device according to claim 1, wherein the hard mask layer comprises amorphous silicon.

4. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer is greater than or equal to 5 nm and less than or equal to 30 nm.

5. The semiconductor device according to claim 1, wherein a channel length of a transistor including the semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.

6. The semiconductor device according to claim 1, wherein a length of the semiconductor layer in a channel length direction is larger than a length of the gate electrode layer in the channel length direction.

7. The semiconductor device according to claim 1, wherein a width of the opening is substantially the same as a length of the semiconductor layer in a channel length direction.

8. The semiconductor device according to claim 1, wherein the semiconductor layer is located over the gate electrode layer.

9. The semiconductor device according to claim 1, wherein the first insulating layer is a protective layer.

10. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer over the gate insulating layer;

a first conductive layer and a second conductive layer over the semiconductor layer;

a third conductive layer over the first conductive layer;

a fourth conductive layer over the second conductive layer; and

a first insulating layer over the third conductive layer and the fourth conductive layer,

wherein a distance between the first conductive layer and the second conductive layer is shorter than a distance between the third conductive layer and the fourth conductive layer, and

wherein the first conductive layer and the third conductive layer serve as a source electrode and the second conductive layer and the fourth conductive layer serve as a drain electrode.

11. The semiconductor device according to claim 10,

wherein the semiconductor layer includes an oxide including In, an element M, and Zn, and

wherein the element M is at least one element selected from the group consisting of Ga, Sn, Hf, Al, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

12. The semiconductor device according to claim 10, wherein a thickness of the semiconductor layer is greater than or equal to 5 nm and less than or equal to 30 nm.

13. The semiconductor device according to claim 10, wherein a channel length of a transistor including the semiconductor layer is greater than or equal to 20 nm and less than or equal to 100 nm.

14. The semiconductor device according to claim 10, wherein a length of the semiconductor layer in a channel length direction is larger than a length of the gate electrode layer in the channel length direction.

15. The semiconductor device according to claim 10, wherein the semiconductor layer is located over the gate electrode layer.

16. The semiconductor device according to claim 10, wherein the first insulating layer is a protective layer.

17. A semiconductor device comprising:

a gate electrode layer adjacent to an oxide semiconductor layer;

the oxide semiconductor layer comprising a channel formation region;

a first conductive layer over and in contact with a first portion of the oxide semiconductor layer;

a second conductive layer over and in contact with a second portion of the oxide semiconductor layer;

a hard mask layer over the first conductive layer and the second conductive layer, wherein an entire upper surface of the hard mask layer is flat; and

a silicon oxynitride film over the hard mask layer,

wherein the silicon oxynitride film is in contact with a third portion of the oxide semiconductor layer between the first portion and the second portion, and

wherein the third portion includes the channel formation region.

18. The semiconductor device according to claim 17,

wherein the oxide semiconductor layer includes In, an element M, and Zn, and

wherein the element M is at least one element selected from the group consisting of Ga, Sn, Hf, Al, Zr, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

19. The semiconductor device according to claim 17, wherein the hard mask layer comprises amorphous silicon.

20. The semiconductor device according to claim 17, wherein a thickness of the oxide semiconductor layer is greater than or equal to 5 nm and less than or equal to 30 nm.

21. The semiconductor device according to claim 17, wherein the oxide semiconductor layer is formed over the gate electrode layer.

22. The semiconductor device according to claim 17, wherein a channel length of a transistor including the oxide semiconductor layer is less than or equal to 30 nm.