High speed, high current, closed loop load transient tester

• US 9,285,412 B2
• Filed: 09/20/2012
• Issued: 03/15/2016
• Est. Priority Date: 09/20/2012
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: Veselic, Mladen
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): PRETLOW, DEMETRIUS R
• Application Number:
  US13/623,284
• Publication Number:
  US 20140077830A1
• Time in Patent Office: 1,272 Days
• Field of Search: 324/750.01, 324/762.09, 324/764.01
• US Class Current: 1/1
• CPC Class Codes: G01R 31/40 Testing power supplies testing photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/50 Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections testing of sparking plugs H01T13/58

Abstract

The present document relates to voltage regulators (101). In particular, the present document relates to the testing of voltage regulators subject to load transients. A test device (110) configured to generate a load current to be drawn at an output of a voltage regulator (101) is described. The test device (110) comprises a load connector (116) for coupling the test device (110) to the output of the voltage regulator (101); a transistor (113) configured to modulate the current through the load connector (116) subject to a control signal (123); wherein the current through the load connector (116) corresponds to the load current; a current sense resistor (112) arranged in series with the transistor (113) and configured to provide a feedback voltage (121) which is substantially proportional to the load current; and an operational amplifier (111) configured to generate the control signal (123) based on the feedback voltage (121) and based on a target voltage (122).

Claims

1. A test device configured to generate a load current to be drawn at an output of a voltage regulator, the test device comprising

a load connector for coupling the test device to the output of the voltage regulator;

a transistor configured to modulate the current through the load connector subject to a control signal;

wherein the current through the load connector corresponds to the load current;

a current sense resistor arranged in series with the transistor and configured to provide a feedback voltage which is substantially proportional to the load current; and

an operational amplifier configured to generate the control signal based on the feedback voltage and based on a target voltage;

wherein the operational amplifier is configured to generate the control signal, such that an absolute difference between the feedback voltage and the target voltage is reduced.

2. The test device of claim 1, further comprising a target load connector configured to couple the test device to an external function generator providing the target voltage.

3. The test device of claim 2, further comprising a voltage divider arranged between the target load connector and an input of the operational amplifier and configured to scale the target voltage provided at the target load connector.

4. The test device of claim 2, further comprising an input termination resistor arranged between the target load connector and an input of the operational amplifier and configured to adapt an impedance of the test device at the target load connector.

5. The test device of claim 1, wherein the transistor is one or more of:

a metal oxide semiconductor field effect transistor; and

an n-type transistor.

6. The test device of claim 1, wherein

the control signal comprises a gate voltage which is applied to a gate of the transistor;

the transistor exhibits a gate capacitance;

the operational amplifier is configured to provide a current corresponding to the gate capacitance within a time interval which is at or below a charging time threshold.

7. The test device of claim 6, wherein the transistor exhibits a rise and/or fall time which is at or below a rise and/or fall time threshold, respectively.

8. The test device of claim 6, wherein a charge of the gate capacitance is at or below 4 nC.

9. The test device of claim 7, wherein the sum of the charging time threshold and the rise and/or fall time threshold is at or below 100 ns.

10. The test device of claim 1, wherein a parasitic inductance of the current sense resistor is at or below an inductance threshold of 10 nH or less.

11. The test device of claim 1, wherein the load connector, the current sense resistor, the transistor and the operational amplifier are arranged on a printed circuit board.

12. The test device of claim 11, wherein the load connector is implemented as a board edge connector which is pluggable into a corresponding female connector of the voltage regulator.

13. The test device of claim 11, wherein the load connector, the transistor and the current sense resistor are arranged such that a conductive path from the load connector, via the transistor and the current sense resistor to ground is at or below a pre-determined path length threshold.

14. The test device of claim 13, wherein the current sense resistor and the transistor are arranged on opposite sides of the printed circuit board.

15. The test device of claim 13, wherein

the transistor is arranged in direct vicinity of the load connector;

and

a drain of the transistor is directly coupled to the load connector.

16. The test device of claim 13, further comprising a heat sink.

17. A system comprising

a voltage regulator;

and

a test device according to claim 1 and configured to generate a test load for the voltage regulator.