Independently selective tile group access with data structuring

• US 9,285,997 B2
• Filed: 10/30/2013
• Issued: 03/15/2016
• Est. Priority Date: 10/30/2013
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Tanzawa, Toru
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US14/067,861
• Publication Number:
  US 20150121000A1
• Time in Patent Office: 867 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of the present disclosure include data structuring techniques and configurations for memory access. In one embodiment, an apparatus includes a plurality of tiles, a plurality of blocks, wherein individual tiles of the plurality of tiles and individual blocks of the plurality of blocks each include a plurality of tile blocks having memory elements and wherein the plurality of tile blocks are accessible for read or write according to a tile address to identify a tile of the plurality of tiles and a block address to identify a block of the plurality of blocks and a data restructuring module configured to modify, based on the tile address, an order of data to be read from or written to the tile blocks. Other embodiments may be described and/or claimed.

Claims

1. An apparatus comprising a three-dimensional (3D) memory array that includes:

a plurality of tiles;

a plurality of blocks, wherein individual tiles of the plurality of tiles and individual blocks of the plurality of blocks each include a plurality of tile blocks having memory elements, wherein the plurality of tile blocks include at least a first array of tile blocks and a second array of tile blocks, wherein the tile blocks are accessible for read or write according to a tile address to identify a tile of the plurality of tiles and a block address to identify a block of the plurality of blocks; and

a data restructuring module to modify, based on the tile address, an order of data to be read from or written to the tile blocks in a first mode at a first point in time and in a second mode at a second point in time that is different than the first point in time, wherein in the first mode data addressed to a first tile of the second array is to be transferred subsequent to transfer of data addressed to the first tile of the first array, data addressed to a second tile of the first array is to be transferred subsequent to transfer of data addressed to the first tile of the second array, and data addressed to the second tile of the second array is to be transferred subsequent to transfer of data addressed to the second tile of the first array, wherein in the second mode only data addressed to the first array is to be transferred and a power supply to the second array is disabled.

2. The apparatus of claim 1, wherein the data restructuring module is to disable tile blocks of one or more tiles of the plurality of tiles that are not identified for read or write access during a read or write operation of one or more other tile blocks.

3. The apparatus of claim 1, wherein:

the data restructuring module is to restructure data into multiple data sets; and

each data set of the multiple data sets has a same data size as an individual tile block of the plurality of tile blocks.

4. The apparatus of claim 3, wherein the data restructuring module is to allocate only tile addresses that are different from one another into each individual data set of the multiple data sets.

5. The apparatus of claim 1, wherein:

in the first mode, no wait period exists between the data addressed to the first tile of the first array and the data addressed to the first tile of the second array.

6. The apparatus of claim 1, wherein:

in the second mode, a single wait period exists between data addressed to the first tile of the first array and subsequent data addressed to the second tile of the first array.

7. The apparatus of claim 1, wherein:

the memory elements comprise multi-level cells of a flash memory die; and

the data restructuring module comprises circuitry of the flash memory die.

8. The apparatus of claim 1, further comprising:

a tile block latch coupled with an individual tile block of the plurality of tile blocks, to select the individual tile blocks for read or write access.

9. The apparatus of claim 8, further comprising:

a wordline coupled with each tile block latch; and

multiple bitlines coupled with each individual tile block of the plurality of tile blocks.

10. A method comprising:

receiving data for read or write access of memory elements of one or more tile blocks of a plurality of tile blocks of a three-dimensional (3D) memory array, wherein the one or more tile blocks are addressable according to a tile address to identify a tile of a plurality of tiles and a block address to identify a block of a plurality of blocks wherein individual tiles of the plurality of tiles and individual blocks of the plurality of blocks each include tile blocks of the plurality of tile blocks, wherein the plurality of tile blocks include at least a first array of tile blocks and a second array of tile blocks; and

modifying, based on the tile address, an order of data to be read from or written to the tile blocks, in a first mode at a first point in time and in a second mode at a second point in time that is different than the first point in time, wherein modifying in the first mode includes arranging for transfer of data addressed to a first tile of the second array subsequent to transferring data addressed to the first tile of the first array, arranging for transfer of data addressed to a second tile of the first array subsequent to transferring data addressed to the first tile of the second array, and arranging for transfer of data addressed to the second tile of the second array subsequent to transferring data addressed to the second tile of the first array, wherein modifying in the second mode includes arranging for transfer of data addressed to the first array and disabling a power supply to the second array.

11. The method of claim 10, wherein modifying, based on the tile address, an order of data comprises restructuring data into multiple data sets, wherein each data set of the multiple data sets has a same data size as an individual tile block of the plurality of tile blocks.

12. The method of claim 11, wherein modifying, based on the tile address, an order of data comprises allocating only tile addresses that are different from one another into each individual data set of the multiple data sets.

13. The method of claim 10, wherein modifying in the first mode, based on the tile address, an order of data comprises:

providing no wait period between the data addressed to the first tile of the first array and the data addressed to the first tile of the second array.

14. The method of claim 10, wherein

modifying in the second mode, based on the tile address, an order of data comprises providing a single wait period between the data addressed to the first tile of the first array and data addressed to the second tile of the first array.

15. The method of claim 10, further comprising:

disabling tile blocks of one or more tiles of the plurality of tiles that are not identified for read or write access during a read or write operation of one or more other tile blocks.

16. The method of claim 10, further comprising:

sending the modified order of data for read or write access of the memory elements.

17. A computing device, comprising:

a three-dimensional (3D) memory array including;

a plurality of tiles, and

a plurality of blocks, wherein individual tiles of the plurality of tiles and individual blocks of the plurality of blocks each include a plurality of tile blocks having memory elements and wherein the plurality of tile blocks include at least a first array of tile blocks and a second array of tile blocks, wherein the tile blocks are accessible for read or write according to a tile address to identify a tile of the plurality of tiles and a block address to identify a block of the plurality of blocks; and

a memory controller having a data restructuring module to modify, based on the tile address, an order of data that is to be transferred to or from the tile blocks in a first mode at a first point in time and in a second mode at a second point in time that is different than the first point in time, wherein in the first mode data addressed to a first tile of the second array is to be transferred immediately subsequent to transfer of data addressed to the first tile of the first array, data addressed to a second tile of the first array is to be transferred subsequent to transfer of data addressed to the first tile of the second array, and data addressed to the second tile of the second array is to be transferred subsequent to transfer of data addressed to the second tile of the first array, wherein in the second mode only data addressed to the first array is to be transferred and a power supply to the second array is disabled.

18. The computing device of claim 17, wherein the memory controller and the memory elements are components of a same die.

19. The computing device of claim 17, further comprising:

random access memory (RAM) coupled with the memory controller and to store information associated with modification of the order of data by the data restructuring module.