Intra-instructional transaction abort handling

• US 9,286,076 B2
• Filed: 10/21/2014
• Issued: 03/15/2016
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Belmar, Brenton F., Farrell, Mark S., Jacobi, Christian, Slegel, Timothy J.
• Primary Examiner(s): Caldwell, Andrew
• Assistant Examiner(s): METZGER, MICHAEL J
• Application Number:
  US14/519,553
• Publication Number:
  US 20150039868A1
• Time in Patent Office: 511 Days
• Field of Search: 712/220
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/466 Transaction processing
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

Claims

1. A method for intra-instructional transaction abort handling comprising:

using, by a processing circuit, an emulation routine to execute an instruction within a transaction, the instruction comprising at least one unit of operation, the transaction effectively delaying committing stores to memory until successful completion of the transaction;

setting a transaction block abort (TXBA) flag based on determining that the emulation of the instruction has made updates to one or more of;

an architected facility and an architected facility buffer, wherein the architected facility buffer comprises one or more rename registers that store data temporarily until instruction completion moves the data to a targeted location; and

based on receiving an abort indication, terminating the emulation of the instruction prior to completing the execution of the instruction, the terminating performed after completing, by the emulation routine, any previously initiated unit of operation of the instruction, wherein the terminating of the emulation of the instruction comprises;

rolling back any storage updates performed during the emulation of the instruction based on determining that the emulation of the instruction has made no updates to the architected facility and no updates to the architected facility buffer;

pausing the terminating of the emulation of the instruction after determining that the TXBA flag is set until all previously initiated units of operation of the instruction of the transaction have completed the emulation;

resetting the TXBA flag based on executing an end of emulation routine instruction or an emulation execution control reset transaction block abort instruction to start a new unit of operation; and

resuming the terminating of the emulation of the instruction based on determining the TXBA flag has been cleared.

2. The method of claim 1, wherein the instruction is a single load instruction (SLI) and the instruction is flushed prior to the at least one unit of operation completing.

3. The method of claim 1, wherein the instruction is a multi-load instruction (MLI), and the executing of the instruction further comprises performing one or more updates to the architected facility buffer.

4. The method of claim 3, further comprising resetting the one or more updates in the architected facility buffer based on receiving the abort indication.

5. The method of claim 1, wherein the instruction is a long load instruction (LLI).

6. The method of claim 5, wherein the LLI makes one or more updates to the architected facility and one or more updates to the architected facility buffer.

7. The method of claim 1, further comprising resetting the one or more updates to the architected facility buffer based on receiving the abort indication;

and retaining the one or more updates to the architected facility in response to the abort indication.

8. A computer program product for intra-instructional transaction abort handling, said computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

using, by the processing circuit, an emulation routine to execute an instruction within a transaction, the instruction comprising at least one unit of operation, the transaction effectively delaying committing stores to memory until successful completion of the transaction;

setting a transaction block abort (TXBA) flag based on determining that the emulation of the instruction has made updates to one or more of;

an architected facility and an architected facility buffer, wherein the architected facility buffer comprises one or more rename registers that store data temporarily until instruction completion moves the data to a targeted location; and

based on receiving an abort indication, terminating the emulation of the instruction prior to completing the execution of the instruction, the terminating performed after completing, by the emulation routine, any previously initiated unit of operation of the instruction, wherein the terminating of the emulation of the instruction comprises;

rolling back any storage updates performed during the emulation of the instruction based on determining that the emulation of the instruction has made no updates to the architected facility and no updates to the architected facility buffer;

pausing the terminating of the emulation of the instruction after determining that the TXBA flag is set until all previously initiated units of operation of the instruction of the transaction have completed the emulation;

resetting the TXBA flag based on executing an end of emulation routine instruction or an emulation execution control reset transaction block abort instruction to start a new unit of operation; and

resuming the terminating of the emulation of the instruction based on determining the TXBA flag has been cleared.

9. The computer program product of claim 8, wherein the instruction is a single load instruction (SLI) and the instruction is flushed prior to the at least one unit of operation completing.

10. The computer program product of claim 8, wherein the instruction is a multi-load instruction (MLI), and the executing of the instruction further comprises performing one or more updates to the architected facility buffer.

11. The computer program product of claim 10, further comprising resetting the one or more updates in the architected facility buffer based on receiving the abort indication.

12. The computer program product of claim 8, wherein the instruction is a long load instruction (LLI).

13. The computer program product of claim 12, wherein the LLI makes one or more updates to the architected facility and one or more updates to the architected facility buffer.

14. The computer program product of claim 8, further comprising resetting the one or more updates to the architected facility buffer based on receiving the abort indication;

and retaining the one or more updates to the architected facility in response to the abort indication.