Word line auto-booting in a spin-torque magnetic memory having local source lines

• US 9,286,218 B2
• Filed: 09/24/2014
• Issued: 03/15/2016
• Est. Priority Date: 03/10/2014
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Andre, Thomas, Alam, Syed M.
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/495,151
• Publication Number:
  US 20150255137A1
• Time in Patent Office: 538 Days
• Field of Search: 365/148, 365/158, 365/203, 365/189.011
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0879 Burst mode
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/5607 using magnetic storage elements
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.

Claims

1. A method for accessing a selected memory cell in a magnetic memory, comprising:

driving a word line to a first word line voltage, wherein the word line is coupled to a set of selection transistors, wherein each selection transistor of the set of selection transistors is coupled between a first electrode of a corresponding memory cell of a set of memory cells and a source line shared by the set of memory cells, wherein the selected memory cell is included in the set of memory cells;

isolating the word line from circuitry used to drive the word line to the first word line voltage to produce an isolated word line; and

driving a plurality of bit lines to a first bit line voltage, wherein each bit line of the plurality of bit lines is coupled to a second electrode of a corresponding memory cell of the set of memory cells, wherein the first bit line voltage is different than the first word line voltage, and wherein driving the plurality of bit lines to the first bit line voltage adjusts voltage on the isolated word line to a second word line voltage.

2. The method of claim 1, wherein the source line is a local source line corresponding to the set of memory cells, and wherein the method further comprises:

driving a selected bit line to a second bit line voltage, wherein the selected bit line is coupled to a second electrode of the selected memory cell, wherein driving the selected bit line to the second bit line voltage results in a first current through the selected memory cell, wherein a fraction of the first current flows through each memory cell coupled to a corresponding bit line of the plurality of bit lines driven to the first bit line voltage.

3. The method of claim 2, wherein the word line corresponds to a row of memory cells that includes the set of memory cells and additional sets of memory cells, and wherein driving the plurality of bit lines further comprises driving additional bit lines to a third bit line voltage, wherein each of the additional bit lines is coupled to a second electrode of a corresponding memory cell included in the additional sets of memory cells in the row to which the word line corresponds.

4. The method of claim 3, wherein the third bit line voltage and the first bit line voltage are about equal.

5. The method of claim 2, further comprising:

after driving the plurality of bit lines to a first bit line voltage, applying a supplemental voltage to the word line.

6. The method of claim 5, wherein the supplemental voltage is about equal to the second word line voltage.

7. The method of claim 5, wherein the supplemental voltage is different in magnitude from the second word line voltage.

8. The method of claim 2, wherein driving the selected bit line to the second bit line voltage results in the first current through the selected memory cell having a magnitude sufficient to write a new state to the selected memory cell, wherein the fraction of the first current is insufficient to write a new state in each of the memory cells coupled to a corresponding bit line of the plurality of bit lines driven to the first bit line voltage.

9. The method of claim 2 further comprising:

decoding a first portion of an address to determine first row selection information;

decoding a second portion of the address to determine second row selection information; and

wherein driving the word line to the first word line voltage includes selecting the first word line based on the first and second row selection information.

10. The method of claim 9 further comprises:

detecting a command corresponding to a bank in the magnetic memory, wherein the bank includes the set of memory cells that includes the selected memory cell; and

sampling the first row selection information based on the command.

11. The method of claim 9 further comprises driving at least one additional word line to a voltage that de-selects the at least one additional word line, wherein driving the at least one additional word line is based on the second row selection information.

12. The method of claim 2, wherein:

driving the word line to the first word line voltage includes driving the word line from an initial word line voltage to the first word line voltage; and

driving the plurality of bit lines to the first bit line voltage includes driving the plurality of bit lines from an initial bit line voltage to the first bit line voltage, wherein the initial word line voltage and the initial bit line voltage are about equal.

13. The method of claim 12, wherein the initial word line voltage and the initial bit line voltage correspond to a ground voltage.

14. A method for accessing a selected memory cell in a magnetic memory, comprising:

driving a word line to a first word line voltage, wherein the word line is coupled to a set of selection transistors, wherein each selection transistor of the set of selection transistors is coupled between a first electrode of a corresponding memory cell of a set of memory cells and a source line shared by the set of memory cells, wherein the selected memory cell is included in the set of memory cells;

isolating the word line from circuitry used to drive the word line to the first word line voltage to produce an isolated word line;

enabling a supplemental voltage provider to adjust a voltage level on the isolated word line to a second word line voltage; and

driving a plurality of bit lines to a first bit line voltage, wherein each bit line of the plurality of bit lines is coupled to a first electrode of a corresponding memory cell of the set of memory cells, wherein the first bit line voltage is different than the first word line voltage, and wherein driving the plurality of bit lines to the first bit line voltage changes the voltage level on the isolated word line to a third word line voltage.

15. The method of claim 14 further comprising:

driving a selected bit line to a second bit line voltage, wherein the selected bit line is coupled to a second electrode of the selected memory cell, wherein driving the selected bit line to the second bit line voltage results in a first current through the selected memory cell, wherein a fraction of the first current flows through each memory cell coupled to a corresponding bit line of the plurality of bit lines driven to the first bit line voltage.

16. The method of claim 14, wherein driving the plurality of bit lines further comprises driving the plurality of bit lines before enabling the supplemental voltage provider.

17. The method of claim 14, wherein the source line is a local source line corresponding to the set of memory cells.

18. The method of claim 17, wherein the word line corresponds to a row of memory cells that includes the set of memory cells and additional sets of memory cells, and wherein driving the plurality of bit lines further comprises driving additional bit lines to a third bit line voltage, wherein each of the additional bit lines is coupled to a second electrode of a corresponding memory cell included in the additional sets of memory cells in the row to which the word line corresponds.

19. The method of claim 14, wherein enabling the supplemental voltage provider further comprises enabling a charge pump.

20. The method of claim 14 further comprising:

decoding a first portion of an address to determine first row selection information;

decoding a second portion of the address to determine second row selection information; and

wherein driving the word line to the first word line voltage includes selecting the first word line based on the first and second row selection information.

21. The method of claim 20 further comprises:

detecting a command corresponding to a bank in the magnetic memory, wherein the bank includes the set of memory cells that includes the selected memory cell; and

sampling the first row selection information based on the command.

22. The method of claim 20 further comprises driving at least one additional word line to a voltage that de-selects the at least one additional word line, wherein driving the at least one additional word line is based on the second row selection information.