Microcontroller programmable system on a chip with programmable interconnect

• US 9,286,254 B2
• Filed: 08/13/2013
• Issued: 03/15/2016
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren S.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US13/966,028
• Publication Number:
  US 20140095757A1
• Time in Patent Office: 945 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25033 structure, control, syncronization, data, alarm, connect I-O line to interface
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Claims

1. An integrated circuit comprising:

a plurality of programmable analog blocks;

a plurality of programmable digital blocks;

a programmable interconnect coupled to at least one of the programmable analog blocks and at least one of the programmable digital blocks;

a programmable Input/Output (I/O) interface coupled to the programmable interconnect and

a plurality of configuration register bits coupled to the programmable I/O interface.

2. The integrated circuit of claim 1, further comprising a programmable system timing block coupled to the programmable interconnect.

3. The integrated circuit of claim 2, wherein the programmable system timing block is configured to provide a clock signal to at least one programmable analog or programmable digital block.

4. The integrated circuit of claim 1, further comprising a temperature sensor coupled to at least one programmable analog block.

5. The integrated circuit of claim 1, wherein the plurality of programmable analog blocks comprise a first programmable analog block type and a second programmable analog block type.

6. The integrated circuit of claim 5, wherein the first programmable analog block type comprises a switched capacitor circuit and the second programmable analog block type comprises a continuous time circuit.

7. The integrated circuit of claim 1, wherein the programmable I/O interface comprises an input bus and an output bus.

8. The integrated circuit of claim 1, wherein the operation of the plurality of programmable analog blocks is controlled by the plurality of programmable register bits.

9. The integrated circuit of claim 1, wherein the operation of the plurality of programmable digital blocks is controlled by the plurality of programmable register bits.

10. The integrated circuit of claim 1, wherein the connectivity of the programmable interconnect is controlled by the plurality of programmable register bits.

11. A method of configuring an integrated circuit comprising:

providing a plurality of programmable analog blocks of a first type;

providing a plurality of programmable digital blocks;

providing a programmable interconnect coupled to at least one of the programmable analog blocks and at least one of the programmable digital blocks;

providing a programmable Input/Output (I/O) interface coupled to the programmable interconnect;

providing a plurality of configuration register bits coupled to the programmable I/O interface and

configuring the plurality of programmable register bits to control the operation of the integrated circuit.

12. The method of claim 11, further comprising providing a programmable system timing block and coupling the programmable system timing block to the programmable interconnect.

13. The method of claim 12, further comprising configuring the programmable system timing block to provide a clock signal to at least one programmable analog or programmable digital block.

14. The method of claim 11, further comprising providing a temperature sensor and coupling the temperature sensor to at least one programmable analog block.

15. The method of claim 11, further comprising providing a plurality of programmable analog blocks of a second type.

16. The method of claim 11, further comprising providing an I/O input bus and an I/O output bus within the I/O interface.

17. The integrated circuit of claim 11, further comprising loading at least some of the programmable register bits with data retrieved from a non-volatile memory.

18. A system comprising:

a microprocessor coupled to a system bus;

a plurality of programmable analog blocks;

a plurality of programmable digital blocks;

a programmable interconnect coupled to at least one of the programmable analog blocks and at least one of the programmable digital blocks and to the system bus;

a programmable Input/Output (I/O) interface coupled to the programmable interconnect and

a plurality of configuration register bits coupled to the system bus.

19. The system of claim 18, further comprising a non-volatile memory coupled to the microprocessor, wherein the microprocessor is configured to retrieve configuration data from the non-volatile memory and load the configuration data into the plurality of configuration register bits.

20. The system of claim 18, further comprising a system timing block coupled to the programmable interconnect and configured to provide a clock signal to at least one programmable digital or programmable analog block.