Thin film transistor array panel and display device including the same

• US 9,286,820 B2
• Filed: 01/31/2014
• Issued: 03/15/2016
• Est. Priority Date: 06/26/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Chang, Jong Woong
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US14/169,475
• Publication Number:
  US 20150001540A1
• Time in Patent Office: 774 Days
• Field of Search: 257/59
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2320/0242 Compensation of deficiencies in the appearance of colours
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A thin film transistor array panel and a display device including the same are disclosed. In one aspect, the thin film transistor array panel includes a plurality of dots located in a display area, each of the plurality of dots including a plurality of pixels, and a plurality of data lines applying data voltages to the plurality of pixels. The thin film transistor array panel also includes a plurality of first dummy data lines located in a first peripheral area of a peripheral area around the display area, the plurality of first dummy data lines are adjacent to a first edge of the display area. The thin film transistor array panel further includes plurality of first data lines applying data voltages to the pixels included in a first dot adjacent to the first edge and are respectively connected to the plurality of first dummy data lines.

Claims

1. A thin film transistor array panel comprising:

a display area including a plurality of pixels;

a peripheral area formed around the display area and including a first peripheral area disposed at a side of the display area;

a plurality of data lines configured to respectively apply a plurality of data voltages to the pixels, the data lines including a plurality of first data lines at least a portion of which is disposed in the display area; and

a plurality of first dummy data lines substantially formed in the first peripheral area and extending along a first boundary edge between the display area and the first peripheral area,

wherein a dot including a plurality of pixels representing different colors from one another has TFTs connected to the first data lines, the dot being adjacent to the first boundary edge, and

wherein each of the first data lines makes a pair with and electrically connected to each one of at least a portion of the first dummy data lines.

2. The thin film transistor array panel of claim 1, wherein the first data lines and the first dummy data lines are electrically connected to each other according to their order of arrangement on the thin film transistor array panel.

3. The thin film transistor array panel of claim 1, further comprising:

a connection part; and

a plurality of connection bridges electrically connecting the first data lines and the first dummy data lines at the connection part.

4. The thin film transistor array panel of claim 3, wherein the connection part is formed in the peripheral area.

5. The thin film transistor array panel of claim 3, wherein the connection bridge is formed in a different layer from that of the first data lines and the first dummy data lines.

6. The thin film transistor array panel of claim 1, further comprising:

a plurality of connection parts; and

a plurality of connection bridges electrically connecting the first data lines and the first dummy data lines at the connection parts.

7. The thin film transistor array panel of claim 6, wherein the connection parts comprise two connection parts formed at respective ends of the first data lines.

8. The thin film transistor array panel of claim 1, wherein the number of the first data lines is equal to or less than the number of the pixels included in the dot.

9. The thin film transistor array panel of claim 1, further comprising:

a dummy pixel electrode formed in the peripheral area.

10. The thin film transistor array panel of claim 9, further comprising:

a light blocking member formed over the dummy pixel electrode and the first dummy data lines.

11. A display device comprising:

a display area including a plurality of pixels;

a peripheral area formed around the display area, the peripheral area including a first peripheral area disposed at a side of the display area;

a plurality of data lines configured to respectively apply a plurality of data voltages to the pixels, the data lines including a plurality of first data lines at least a portion of which is disposed in the display area; and

a plurality of first dummy data lines substantially formed in the first peripheral area and extending along a first boundary edge between the display area and the first peripheral area,

wherein a dot including a plurality of pixels representing different colors from one another have TFTs connected to the first data lines, the dot being adjacent to the first boundary edge, and

wherein each of the plurality of first data lines makes a pair with and electrically connected to each one of at least a portion of the first dummy data lines.

12. The display device of claim 11, wherein the first data lines and the first dummy data lines are electrically connected to each other according to their order of arrangement.

13. The display device of claim 11, further comprising

a connection part;

and

a plurality of connection bridges formed at the connection part, wherein the first data lines and the first dummy data lines are electrically connected to each other through the connection bridges.

14. The display device of claim 13, wherein the connection part is formed in the peripheral area.

15. The display device of claim 13, wherein the connection bridges are formed in a different layer from that of the first data lines and the first dummy data lines.

16. The display device of claim 11, further comprising:

a light blocking member formed over the peripheral area.